Abstract:
For single-level cell flash memories and multi-level cell flash memories, different operations can be performed according to their stability when an abnormal status is terminated. Specifically, for the multi-level cell flash memories, when the abnormal status is terminated, a now physical block is used to proceed with write operation, and the previous physical block(s) would not be written any more. On the contrary, for the single-level cell flash memories, when the abnormal status is terminated, the controller needs to perform corresponding operations on the last physical page of the previous physical block(s).
Abstract:
The invention introduces a method for GC (garbage collection) POR (Power Off Recovery), performed by a processing unit, including at least the following steps: after a reboot subsequent to a power-off event, reading a GC recovery flag from a storage unit and determining whether the GC recovery flag indicates that a flash memory needs a POR; and, when the GC recovery flag indicates that the flash memory needs a POR, programming dummy data into a predefined number of empty pages next to the last programmed page of a destination block of the storage unit and performing an unfinished GC data-access operation.
Abstract:
A data storage device is provided. The data storage device includes a flash memory and a controller. The flash memory includes a plurality of blocks. Each block includes a plurality of pages. when the data storage device is resumed from a power-off event, the controller selects a first block which was written last before the power-off event among the plurality of blocks and writes data of a plurality of first pages of the first block into a plurality of second pages of the first block.
Abstract:
A data storage device with a FLASH memory accessed via multiple channels and a FLASH memory control method are disclosed. The control method includes dividing a plurality of blocks of a FLASH memory into groups to be accessed by a plurality of channels separately, each block comprising a plurality of pages; allocating a random access memory to provide a first set of cache spaces for the different ones of the plurality of channels; separating write data issued from a host to correspond to the plurality of channels; and after data arrangement in the first set of cache spaces for every channel is completed, writing data arranged in the first set of cache spaces for every channel to the FLASH memory via the plurality of channels. The control method further includes allocating the random access memory to provide a second set of cache spaces; and using the second set of cache spaces to perform data arrangement for the write data issued from the host when writing the data arranged in the first set of cache spaces for every channel to the FLASH memory.
Abstract:
In recovery operations performed after non-volatile memory devices (i.e., flash memories and so on) experience abnormal status, when unstable data pages are found, valid data pages are copied to another physical block from the original physical block directly and the original physical block is not utilized any more, in order to prevent from spreading error. Further, in order to accelerate the determination process, only partial data of a page is read and whether the page is a valid page is determined based on statistic, when finding out which page is a valid page.
Abstract:
A data storage device and a FLASH memory control method with a cache space. The FLASH memory control method includes the following steps: using a plurality of channels to access a FLASH memory, wherein the FLASH memory has a plurality of blocks each with a plurality of pages, and the blocks are grouped to be accessed by the different channels; allocating a random access memory to provide a cache space, the cache space having a plurality of cache areas caching write data for the different channels, respectively; distributing the data issued from a host to correspond to the different channels; and reusing a latest-updated cache area of the cache space to cache write data when a logical address requested to be written with data is identical to a logical address that the latest-updated cache area corresponds to.