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    Checkpointing user design states in a configurable IC
    31.
    发明授权
    Checkpointing user design states in a configurable IC 有权
    在可配置IC中检查用户设计状态

    公开(公告)号：US07512850B2

    公开(公告)日：2009-03-31

    申请号：US11375370

    申请日：2006-03-13

    申请人： Jason Redgrave ,  Brad Hutchings ,  Herman Schmit ,  Steven Teig ,  Tom Kronmiller

    发明人： Jason Redgrave ,  Brad Hutchings ,  Herman Schmit ,  Steven Teig ,  Tom Kronmiller

    IPC分类号： G01R31/28

    CPC分类号： H03K19/1731 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/17764

    摘要： Some embodiments provide a configurable integrated circuit (IC) that has several configurable circuits and several user design state (UDS) circuits. The UDS circuits store user-design state values. The configurable IC also includes a debug network communicatively coupled to the UDS circuits. The debug network is for retrieving the user-design state values of several UDS circuits at various stoppages of the operation of the IC without retrieving configuration data that is used to configure the configurable circuits of the IC. The retrieved user-design state values at each stoppage are used as the checkpointed state of the IC while debugging the IC. In some embodiments, the debug network allows the checkpointing of only certain portions of the configurable IC.

    摘要翻译： 一些实施例提供了具有多个可配置电路和几个用户设计状态（UDS）电路的可配置集成电路（IC）。 UDS电路存储用户设计状态值。 可配置IC还包括通信地耦合到UDS电路的调试网络。 调试网络用于在IC的操作的各种停止状态下检索多个UDS电路的用户设计状态值，而不检索用于配置IC的可配置电路的配置数据。 在调试IC时，将每个停止时检索到的用户设计状态值用作IC的检查点状态。 在一些实施例中，调试网络允许只对可配置IC的某些部分进行检查点。

    RUNTIME LOADING OF CONFIGURATION DATA IN A CONFIGURABLE IC
    32.
    发明申请
    RUNTIME LOADING OF CONFIGURATION DATA IN A CONFIGURABLE IC 有权
    在配置IC中运行配置数据

    公开(公告)号：US20080272801A1

    公开(公告)日：2008-11-06

    申请号：US11375364

    申请日：2006-03-13

    申请人： Brad Hutchings ,  Jason Redgrave ,  Teju Khubchandani ,  Herman Schmit ,  Steven Teig

    发明人： Brad Hutchings ,  Jason Redgrave ,  Teju Khubchandani ,  Herman Schmit ,  Steven Teig

    IPC分类号： H03K19/173 ,  H03K19/177

    CPC分类号： H03K19/1731 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/17764

    摘要： Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network. Also, the IC of some embodiments includes a configuration controller for retrieving configuration data from outside of the IC, formulating configuration data sets, and routing the configuration data sets to the second set of configurable circuits over the configuration network.

    摘要翻译： 本发明的一些实施例提供了一种可配置集成电路（IC），其具有用于可配置地执行不同操作的多个可配置电路。 在IC的操作期间，每个特定可配置电路执行由针对特定可配置电路的特定配置数据集指定的特定操作。 当IC操作并且第一组可配置电路执行第一组操作时，从IC的外部加载配置数据，用于配置第二组可配置电路。 在一些实施例中，可配置IC包括用于从IC外部快速加载IC中的配置数据的配置网络。 在这些实施例中的一些实施例中，配置网络是流水线网络。 此外，一些实施例的IC包括用于从IC外部检索配置数据的配置控制器，配置数据组，以及通过配置网络将配置数据集路由到第二组可配置电路。

    Configurable IC's with configurable logic resources that have asymetric inputs and/or outputs
    35.
    发明授权
    Configurable IC's with configurable logic resources that have asymetric inputs and/or outputs 有权

    公开(公告)号：US07259587B1

    公开(公告)日：2007-08-21

    申请号：US11081861

    申请日：2005-03-15

    申请人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang ,  Jason Redgrave

    发明人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang ,  Jason Redgrave

    IPC分类号： H03K19/177 ,  H01L25/00

    CPC分类号： H01L25/065 ,  H01L27/0207 ,  H01L27/11803 ,  H01L27/11898 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K19/17736 ,  H03K19/17796 ,  H01L2924/00014 ,  H01L2924/00

    摘要： Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. In some embodiments, each configurable interior tile includes a set of configurable logic circuits, a set of configurable input-select circuits for selecting inputs to the configurable logic circuits, and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable input-select circuits in each interior tile has a set of inputs that are supplied by a set of asymmetric locations in the configurable IC. Any distance between any input-select circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular input-select circuit in any interior tile and any circuit that provides an input to the particular input-select circuit. Also, in some embodiments, each configurable interior tile includes a set of configurable logic circuits and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable logic circuits in each interior tile has a set of outputs that are supplied to a set of asymmetric locations in the configurable IC. Any distance between any logic circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular logic circuit in any interior tile and any circuit that receives an output of the particular logic circuit. In some embodiments, the set of asymmetric locations is a set of locations that includes at least one location that has no symmetrical relationship with any other location in the set. In some embodiments, each input-select circuit has at least one output that is supplied to one configurable logic circuit.

    Accessing Multiple User States Concurrently in a Configurable IC
    37.
    发明申请
    Accessing Multiple User States Concurrently in a Configurable IC 有权
    在可配置IC中同时访问多个用户状态

    公开(公告)号：US20110060896A1

    公开(公告)日：2011-03-10

    申请号：US12870779

    申请日：2010-08-27

    申请人： Jason Redgrave ,  Brad Hutchings ,  Steven Teig ,  Herman Schmit ,  Teju Khubchandani

    发明人： Jason Redgrave ,  Brad Hutchings ,  Steven Teig ,  Herman Schmit ,  Teju Khubchandani

    IPC分类号： H03K19/00

    CPC分类号： H03K19/1731 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/17764

    摘要： Some embodiments of the invention provide a configuration/debug network for configuring and debugging a configurable integrated circuit (IC). The configurable IC in some embodiments includes configurable resources (e.g., configurable logic resources, routing resources, memory resources, etc.) that can be grouped in conceptual configurable tiles that are arranged in several rows and columns. Some embodiments allow tiles to be individually addressed, globally addressed (i.e., all addressed together), or addressed based on their tile types. The configurable IC includes numerous user-design state elements (“UDS elements”) in some embodiments. In some embodiments, the configuration/debug network has a streaming mode that can direct various circuits in one or more configurable tiles to stream out their data during the operation of the configurable IC. Accordingly, in the embodiments where the configuration/debug network connects to some or all of the UDS elements, the configurable/debug network can be used in a streaming mode to stream out data from the UDS elements of the tiles, in order to identify any errors in the operation of the IC. In other words, the streaming of the data from the UDS elements can be used to debug the operation of the configurable IC. In some embodiments, the configuration/debug network has a broadcasting mode that can direct various resources (e.g., memories, storage elements, etc.) in one or more configurable tiles to store the same data. For instance, the broadcasting mode can be used to initialize the memory blocks in the configurable memory tiles.

    摘要翻译： 本发明的一些实施例提供了用于配置和调试可配置集成电路（IC）的配置/调试网络。 在一些实施例中，可配置IC包括可被分组在以多行和列排列的概念可配置瓦片中的可配置资源（例如，可配置逻辑资源，路由资源，存储器资源等）。 一些实施例允许瓦片被单独寻址，全局寻址（即，全部寻址在一起）或基于它们的瓦片类型寻址。 在一些实施例中，可配置IC包括许多用户设计状态元件（“UDS元件”）。 在一些实施例中，配置/调试网络具有流模式，其可以在一个或多个可配置瓦片中引导各种电路以在可配置IC的操作期间流出其数据。 因此，在配置/调试网络连接到一些或所有UDS元件的实施例中，可配置/调试网络可以以流模式用于从瓦片的UDS元件流出数据，以便识别任何 IC的运行错误。 换句话说，来自UDS元件的数据流可用于调试可配置IC的操作。 在一些实施例中，配置/调试网络具有可以将一些或多个可配置瓦片中的各种资源（例如，存储器，存储元件等）引导以存储相同数据的广播模式。 例如，可以使用广播模式来初始化可配置存储器块中的存储器块。

    Runtime loading of configuration data in a configurable IC
    38.
    发明授权
    Runtime loading of configuration data in a configurable IC 有权
    可配置IC中的配置数据的运行时加载

    公开(公告)号：US07492186B2

    公开(公告)日：2009-02-17

    申请号：US11375364

    申请日：2006-03-13

    申请人： Brad Hutchings ,  Jason Redgrave ,  Teju Khubchandani ,  Herman Schmit ,  Steven Teig

    发明人： Brad Hutchings ,  Jason Redgrave ,  Teju Khubchandani ,  Herman Schmit ,  Steven Teig

    IPC分类号： G06F7/38 ,  H03K19/173

    CPC分类号： H03K19/1731 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/17764

    摘要： Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network. Also, the IC of some embodiments includes a configuration controller for retrieving configuration data from outside of the IC, formulating configuration data sets, and routing the configuration data sets to the second set of configurable circuits over the configuration network.

    摘要翻译： 本发明的一些实施例提供了一种可配置集成电路（IC），其具有用于可配置地执行不同操作的多个可配置电路。 在IC的操作期间，每个特定可配置电路执行由针对特定可配置电路的特定配置数据集指定的特定操作。 当IC操作并且第一组可配置电路执行第一组操作时，从IC的外部加载配置数据，用于配置第二组可配置电路。 在一些实施例中，可配置IC包括用于从IC外部快速加载IC中的配置数据的配置网络。 在这些实施例中的一些实施例中，配置网络是流水线网络。 此外，一些实施例的IC包括用于从IC外部检索配置数据的配置控制器，配置数据组，以及通过配置网络将配置数据集路由到第二组可配置电路。

    Random access of user design states in a configurable IC
    39.
    发明申请
    Random access of user design states in a configurable IC 有权
    可配置IC中用户设计状态的随机访问

    公开(公告)号：US20080272802A1

    公开(公告)日：2008-11-06

    申请号：US11375561

    申请日：2006-03-13

    申请人： Brad Hutchings ,  Jason Redgrave ,  Steven Teig ,  Herman Schmit

    发明人： Brad Hutchings ,  Jason Redgrave ,  Steven Teig ,  Herman Schmit

    IPC分类号： H03K19/173

    CPC分类号： H03K19/1731 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/17764

    摘要： Some embodiments of the invention is a configurable integrated circuit (IC) that includes (1) several configurable logic circuits, (2) a first routing network for connecting the configurable logic circuits, (3) several user design state (UDS) circuits, and (4) a second network communicatively coupled to the UDS circuits. In least one period during the operation of the IC, the second network receives addresses for a several UDS circuits in a random access manner. In some embodiments, the second network is a debug network for reading randomly state values stored by the addressed UDS circuits during the user-design operation of the IC.

    摘要翻译： 本发明的一些实施例是可配置集成电路（IC），其包括（1）几个可配置逻辑电路，（2）用于连接可配置逻辑电路的第一路由网络，（3）几个用户设计状态（UDS）电路和 （4）通信地耦合到所述UDS电路的第二网络。 在IC操作期间的至少一个周期中，第二网络以随机存取的方式接收几个UDS电路的地址。 在一些实施例中，第二网络是用于在IC的用户设计操作期间读取由寻址的UDS电路存储的随机状态值的调试网络。