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公开(公告)号：US20220359544A1
公开(公告)日：2022-11-10
申请号：US17873236
申请日：2022-07-26
Inventor： Rainer Yen-Chieh Huang , Hai-Ching Chen , Chung-Te Lin
IPC: H01L27/1159 , H01L21/28 , H01L29/51 , H01L23/522 , H01L29/66 , H01L29/78
Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode arranged over a substrate. A gate dielectric layer is arranged over the gate electrode, and an active structure is arranged over the gate dielectric layer. A source contact and a drain contact are arranged over the active structure. The active structure includes a stack of cocktail layers alternating with first active layers. The cocktail layers include a mixture of a first material and a second material. The first active layers include a third material that is different than the first and second materials. The bottommost layer of the active structure is one of the cocktail layers.
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公开(公告)号：US20220336733A1
公开(公告)日：2022-10-20
申请号：US17463985
申请日：2021-09-01
Inventor： Yu-Feng Yin , Min-Kun Dai , Chien-Hua Huang , Chung-Te Lin
Abstract: Semiconductor structure and methods of forming the same are provided. An exemplary method includes providing a substrate having a first region and a second region, forming an array of memory cells over the first region of the substrate, and forming a memory-level dielectric layer around the array of memory cells. Each of the memory cells includes, from bottom to top, a bottom electrode, a memory material layer stack, and a top electrode. The exemplary method also includes forming a metal line directly interfacing a respective row of top electrodes of the array of memory cells. The metal line also directly interfaces a top surface of the memory-level dielectric layer.
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公开(公告)号：US20200006217A1
公开(公告)日：2020-01-02
申请号：US16563215
申请日：2019-09-06
Inventor： Tung-Heng Hsieh , Ting-Wei Chiang , Chung-Te Lin , Hui-Zhong Zhuang , Li-Chun Tien , Sheng-Hsiung Wang
IPC: H01L23/528 , H01L23/535 , H01L27/088 , H01L29/40 , H01L21/768 , H01L21/8234 , H01L23/485
Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.
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公开(公告)号：US20180337167A1
公开(公告)日：2018-11-22
申请号：US16051241
申请日：2018-07-31
Inventor： Chung-Te Lin , Ting-Wei Chiang , Hui-Zhong Zhuang , Pin-Dai Sue , Li-Chun Tien
IPC: H01L27/02 , H01L29/423 , G06F17/50 , H01L27/092 , H01L27/118
CPC classification number: H01L27/0207 , G06F17/5072 , H01L27/092 , H01L29/42376 , H01L2027/11875
Abstract: A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.
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公开(公告)号：US09899263B2
公开(公告)日：2018-02-20
申请号：US15150149
申请日：2016-05-09
Inventor： Tung-Heng Hsieh , Chung-Te Lin , Sheng-Hsiung Wang , Hui-Zhong Zhuang , Min-Hsiung Chiang , Ting-Wei Chiang , Li-Chun Tien
IPC: G06F17/50 , H01L21/8234 , H01L27/02 , H01L21/304 , H01L29/66 , H01L21/3213 , H01L27/118
CPC classification number: H01L21/82345 , G06F17/5072 , H01L21/3043 , H01L21/32139 , H01L21/823431 , H01L27/0207 , H01L27/11807 , H01L29/66545 , H01L29/66795
Abstract: A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.
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Patent Agency Ranking
公开(公告)号：US09412700B2
公开(公告)日：2016-08-09
申请号：US14515276
申请日：2014-10-15
Inventor： Tung-Heng Hsieh , Hui-Zhong Zhuang , Chung-Te Lin , Ting-Wei Chiang , Sheng-Hsiung Wang , Li-Chun Tien
IPC: H01L27/088 , H01L23/535 , H01L29/40 , H01L21/768
CPC classification number: H01L23/528 , H01L21/76895 , H01L21/76897 , H01L21/823475 , H01L23/485 , H01L23/535 , H01L27/088 , H01L29/401 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.
Abstract translation: 半导体器件包括具有有源区的衬底，衬底顶表面上的第一栅极结构，衬底顶表面上的第二栅极结构，第一栅极结构的每个侧壁上的一对第一间隔物， 在所述第二栅极结构的每个侧壁上的一对第二间隔物，至少所述第一栅极结构上的绝缘层，所述有源区上的第一导电特征和所述衬底上的第二导电特征。 此外，第二栅极结构与第一栅极结构相邻，并且第一导电特征的顶表面与第二导电特征的顶表面共面。
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公开(公告)号：US12288820B2
公开(公告)日：2025-04-29
申请号：US18510506
申请日：2023-11-15
Inventor： Hung-Chang Sun , Sheng-Chih Lai , Yu-Wei Jiang , Kuo-Chang Chiang , TsuChing Yang , Feng-Cheng Yang , Chung-Te Lin
Abstract: A transistor includes an insulating layer, a source region, a drain region, a channel layer, a ferroelectric layer, and a gate electrode. The source region and the drain region are respectively disposed on and in physical contact with two opposite sidewalls of the insulating layer. A thickness of the source region, a thickness of the drain region, and a thickness of the insulating layer are substantially the same. The channel layer is disposed on the insulating layer, the source region, and the drain region. The ferroelectric layer is disposed over the channel layer. The gate electrode is disposed on the ferroelectric layer.
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公开(公告)号：US12274070B2
公开(公告)日：2025-04-08
申请号：US17857047
申请日：2022-07-04
Inventor： Po-Ting Lin , Wei-Chih Wen , Kai-Wen Cheng , Wu-Wei Tsai , Yu-Ming Hsiang , Yan-Yi Chen , Hai-Ching Chen , Yu-Ming Lin , Chung-Te Lin
IPC: H01L29/78 , H01L23/522 , H01L23/528 , H01L29/51 , H01L29/66 , H10B53/20
Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.
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公开(公告)号：US12274068B2
公开(公告)日：2025-04-08
申请号：US17740331
申请日：2022-05-09
Inventor： Rainer Yen-Chieh Huang , Han-Ting Tsai , Tsann Lin , Kuo-Chang Chiang , Min-Kun Dai , Chung-Te Lin
Abstract: Provided is a method of forming a ferroelectric memory device including: forming a ferroelectric layer between a gate electrode and a channel layer by a first atomic layer deposition (ALD) process. The first ALD process includes: providing a first precursor during a first section; and providing a first mixed precursor during a second section, wherein the first mixed precursor includes a hafnium-containing precursor and a zirconium-containing precursor. In this case, the ferroelectric layer is directly formed as Hf0.5Zr0.5O2 with an orthorhombic phase (O-phase) to enhance the ferroelectric polarization and property.
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公开(公告)号：US12268005B2
公开(公告)日：2025-04-01
申请号：US18518579
申请日：2023-11-23
Inventor： Sheng-Chih Lai , Chung-Te Lin
IPC: H10B43/35 , H01L23/522 , H10B43/10 , H10B43/20
Abstract: A semiconductor structure includes a plurality of memory cells stacked up along a first direction. Each of the memory cells include a memory stack, connecting lines, and insulating layers. The memory stack includes a first dielectric layer, a channel layer disposed on the first dielectric layer, a charge trapping layer disposed on the channel layer, a second dielectric layer disposed on the charge trapping layer, and a gate layer disposed in between the channel layer and the second dielectric layer. The connecting lines are extending along the first direction and covering side surfaces of the memory stack. The insulating layers are extending along the first direction, wherein the insulating layers are located aside the connecting lines and covering the side surfaces of the memory stack.
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