公开(公告)号：US20240431116A1

公开(公告)日：2024-12-26

申请号：US18338414

申请日：2023-06-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Chang Chiang ,  Chung-Te Lin ,  Yu-Ming Lin ,  Po-Ting Lin ,  Yu-Chuan Shih

IPC: H10B51/30 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: The present disclosure relates a ferroelectric field-effect transistor (FeFET) device. The FeFET device includes a ferroelectric structure having a first side and a second side. A gate structure is disposed along the first side of the ferroelectric structure, and an oxide semiconductor is disposed along the second side of the ferroelectric structure. The oxide semiconductor has a first semiconductor type. A source region and a drain region are disposed on the oxide semiconductor. The gate structure is laterally between the source region and the drain region. A polarization enhancement structure is arranged on the oxide semiconductor between the source region and the drain region. The polarization enhancement structure includes a semiconductor material or an oxide semiconductor material having a second semiconductor type that is different than the first semiconductor type.

公开(公告)号：US12150309B2

公开(公告)日：2024-11-19

申请号：US17591174

申请日：2022-02-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Po-Ting Lin ,  Song-Fu Liao ,  Hai-Ching Chen ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H10B51/30

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure.

公开(公告)号：US20240379870A1

公开(公告)日：2024-11-14

申请号：US18316439

申请日：2023-05-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wu-Wei Tsai ,  Hai-Ching Chen ,  Po-Ting Lin ,  Yan-Yi Chen ,  Yu-Ming Lin ,  Chung-Te Lin ,  Tzer-Min Shen ,  Yen-Tien Tung

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66

Abstract: The problem of providing transistors that can be manufactured to any specified threshold voltage withing a broad range of threshold voltages without creating leakage, capacitance, or process compatibility issues is solved by introducing a buried layer of a second dielectric composition into a gate dielectric of a first dielectric composition. The second dielectric composition is selected relative to the first dielectric composition so that dipoles form around the interface of the two dielectrics. The dipoles create an electric field that causes a shift in the threshold voltage. The buried layer has a higher dielectric constant than the gate dielectric, is thinner than the gate dielectric, and is proximate the channel.

公开(公告)号：US20230369420A1

公开(公告)日：2023-11-16

申请号：US18357264

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Po-Ting Lin ,  Song-Fu Liao ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H10B51/00

CPC classification number: H01L29/40111 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/00

Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC). The IC includes a substrate and an electrode disposed over the substrate. A ferroelectric layer is vertically stacked with the electrode. A seed layer that includes oxygen is vertically stacked between the electrode and the ferroelectric layer. The ferroelectric layer has a substantially uniform orthorhombic crystalline phase.

公开(公告)号：US20230247841A1

公开(公告)日：2023-08-03

申请号：US17591174

申请日：2022-02-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Po-Ting Lin ,  Song-Fu Liao ,  Hai-Ching Chen ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L27/1159 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/1159 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/6656 ,  H01L29/42324

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) comprising a lower gate electrode disposed in a dielectric structure. A first ferroelectric structure overlies the lower gate electrode. A first floating electrode structure overlies the first ferroelectric structure. A channel structure overlies the first floating electrode structure. A second floating electrode structure overlies the channel structure. A second ferroelectric structure overlies the second floating electrode structure. An upper gate electrode overlies the second ferroelectric structure.

公开(公告)号：US20240145571A1

公开(公告)日：2024-05-02

申请号：US18150259

申请日：2023-01-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Ting Lin ,  Yu-Ming Hsiang ,  Wei-Chih Wen ,  Yin-Hao Wu ,  Wu-Wei Tsai ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/51 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H10B51/30

CPC classification number: H01L29/516 ,  H01L21/02178 ,  H01L21/02194 ,  H01L21/0228 ,  H01L29/66969 ,  H01L29/78391 ,  H10B51/30

Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.

公开(公告)号：US20240055517A1

公开(公告)日：2024-02-15

申请号：US17886472

申请日：2022-08-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Chang Chiang ,  Yu-Chuan Shih ,  Chun-Chieh Lu ,  Po-Ting Lin ,  Hai-Ching Chen ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/78 ,  H01L27/1159 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L27/1159 ,  H01L29/516 ,  H01L29/6684

Abstract: Provided are a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (S/D) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.

公开(公告)号：US20240006538A1

公开(公告)日：2024-01-04

申请号：US17857021

申请日：2022-07-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wu-Wei Tsai ,  Po-Ting Lin ,  Kai-Wen Cheng ,  Sai-Hooi Yeong ,  Han-Ting Tsai ,  Ya-Ling Lee ,  Hai-Ching Chen ,  Chung-Te Lin ,  Yu-Ming Lin

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/1159

CPC classification number: H01L29/7869 ,  H01L29/66742 ,  H01L27/1159

Abstract: A method of forming a semiconductor device is provided. A gate electrode is formed within an insulating layer that overlies a substrate. A gate dielectric layer is formed over the gate electrode. A first oxide semiconductor layer is formed over the gate dielectric layer. A dielectric layer is formed over the first oxide semiconductor layer. The dielectric layer and the first oxide semiconductor layer are patterned, so as to form first and second openings that expose portions of the gate dielectric layer. An interfacial layer is conformally formed on sidewalls and bottoms of the first and second openings. A second oxide semiconductor layer is formed over the interfacial layer in the first and second openings. A metal layer is formed over the second oxide semiconductor layer in the first and second openings.

公开(公告)号：US20230268438A1

公开(公告)日：2023-08-24

申请号：US18308791

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Po-Ting Lin ,  Hai-Ching Chen ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/49 ,  H10B51/20

CPC classification number: H01L29/78391 ,  H01L29/78693 ,  H01L29/78642 ,  H01L29/4908 ,  H10B51/20

Abstract: A semiconductor device is described. The semiconductor device includes a substrate and a metal layer disposed on the substrate. A seed layer is formed on the metal layer. A ferroelectric gate layer is formed on the seed layer. A channel layer is formed over the ferroelectric gate layer. The seed layer is arranged to increase the orthorhombic phase fraction of the ferroelectric gate layer.

公开(公告)号：US20230143625A1

公开(公告)日：2023-05-11

申请号：US17570028

申请日：2022-01-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Po-Ting Lin ,  Song-Fu Liao ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11585

CPC classification number: H01L29/40111 ,  H01L29/6684 ,  H01L29/78391 ,  H01L27/11585

Abstract: In some embodiments, the present disclosure relates to a method for forming an integrated circuit (IC), including forming a first electrode layer having a first metal over a substrate, performing a first atomic layer deposition (ALD) pulse that exposes the first electrode layer to oxygen atoms, exposing the first electrode layer to a first temperature, the first temperature causing the first electrode layer to react with the oxygen atoms to form a seed structure over the first electrode layer, and performing a series of ALD pulses at a second temperature to form a ferroelectric structure over the seed structure. The second temperature is less than the first temperature and the ferroelectric structure is configured to store a data state.