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公开(公告)号：US11552069B1
公开(公告)日：2023-01-10
申请号：US17463241
申请日：2021-08-31
IPC分类号： H01L27/02 , G06F1/3287
摘要： An integrated circuit includes a first, second and third power rail, and a header circuit coupled to a gated circuit. The gated circuit is configured to operate on a first or second voltage. The first and second power rail are on a back-side of a wafer, and extend in a first direction. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The second power rail is separated from the first power rail in a second direction. The second power rail is configured to supply the second voltage to the gated circuit. The third power rail is on a front-side of the wafer and includes a first set of conductors extending in the second direction, and separated in the first direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit.
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公开(公告)号：US11227093B2
公开(公告)日：2022-01-18
申请号：US17157765
申请日：2021-01-25
发明人： Kuo-Nan Yang , Wan-Yu Lo , Chung-Hsing Wang , Hiranmay Biswas
IPC分类号： G06F30/398 , G06F30/392 , G06F30/394
摘要： A method of forming a semiconductor device includes: providing a first circuit having a plurality of circuit cells; analyzing a loading capacitance on a first pin cell connecting a first circuit cell and a second circuit cell in the plurality of circuit cells to determine if the loading capacitance of the first pin cell is larger than a first predetermined capacitance; replacing the first pin cell by a second pin cell for generating a second circuit when the loading capacitance is larger than the first predetermined capacitances, wherein the second pin cell is different from the first pin cell; and generating the semiconductor device according to the second circuit.
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公开(公告)号：US11157677B2
公开(公告)日：2021-10-26
申请号：US16698308
申请日：2019-11-27
发明人： Hiranmay Biswas , Chung-Hsing Wang , Kuo-Nan Yang , Yi-Kan Cheng
IPC分类号： G06F30/394 , H01L27/02 , G06F30/398 , H01L27/118 , G06F119/06
摘要： A method of a layout diagram (of a conductive line structure for an IC) including: for a first set of pillar patterns included in an initial layout diagram that represents portions of an M(i) layer of metallization and where i is a non-negative number, the first set including first and second pillar patterns which are non-overlapping of each other, which have long axes that are substantially collinear with a reference line, and which have a first distance of separation, determining a first distance of separation as between corresponding immediately adjacent members of the first set; recognizing that the first distance is less than a transverse routing (TVR) separation threshold for an M(i+j) layer of metallization, where j is an integer and j≥2; and increasing the first distance so as to become a second distance which is greater than the TVR separation threshold of the M(i+j) layer.
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34.发明授权公开(公告)号：US11087063B2
公开(公告)日：2021-08-10
申请号：US16405883
申请日：2019-05-07
发明人： Ritesh Kumar , Chung-Hsing Wang , Kuo-Nan Yang , Hiranmay Biswas , Shu-Yi Ying
IPC分类号： G06F30/394 , G06F30/398
摘要： A method (of revising an initial layout diagram of a wire routing arrangement) includes: identifying, in a first conductance layer of the initial layout diagram, a routed pattern and a dummy pattern, each of which extends in a first direction; the routed patterns being functional in a representation of a circuit; the dummy patterns being non-functional in the representation of the circuit; and revising to form a revised layout diagram, the revising including adding first and second jumper patterns, into a second conductance layer, which extend in a second direction substantially perpendicular to the first direction, and adding via patterns, into an interconnection layer between the first and second conductance layers, which represent (A) connections between the first jumper pattern and first ends of the corresponding routed and dummy patterns, and (B) connections between the second jumper pattern and second ends of the corresponding routed and dummy patterns.
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公开(公告)号：US10997347B2
公开(公告)日：2021-05-04
申请号：US16577457
申请日：2019-09-20
发明人： Wan-Yu Lo , Chung-Hsing Wang , Chin-Shen Lin , Kuo-Nan Yang
IPC分类号： G06F30/398 , G06F30/392 , G06F111/10 , G06F111/20 , G06F119/08
摘要： In a method, based on an operating condition of a region of an integrated circuit (IC), a first relationship between a temperature and heating power of the region is determined. Based on a cooling capacity of the region, a second relationship between the temperature and cooling power of the region is determined. Based on the first relationship and the second relationship, it is determined whether the region is thermally stable. In response to a determination that the region is thermally unstable, at least one of a structure or the operating condition of the region is changed. At least one of the determination of the first relationship, the determination of the second relationship, the determination of thermally stability of the region, or the change of at least one of the structure or the operating condition of the region is executed by a processor.
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公开(公告)号：US10977415B2
公开(公告)日：2021-04-13
申请号：US16870386
申请日：2020-05-08
IPC分类号： G06F30/394 , H01L23/528 , H01L27/02 , H01L27/118 , G06F111/04 , G06F111/20 , G06F119/18
摘要： A method for forming an integrated device includes following operations. It is provided a first circuit having a first connecting path in a metal line layer, a second connecting path, and a third connecting path. The second connecting path is electrically connected to a first connecting portion of the first connecting path in the metal line layer. The third connecting path is electrically coupled to a second connecting portion of the first connecting path in the metal line layer. An electromigration (EM) data of the first connecting path is analyzed to determine if a third connecting portion in the metal line layer between the first connecting portion and the second connecting portion induces EM phenomenon. The first circuit is modified to generate a second circuit when the third connecting portion induces EM phenomenon. The integrated device is generated according to the second circuit.
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公开(公告)号：US10664641B2
公开(公告)日：2020-05-26
申请号：US15933785
申请日：2018-03-23
IPC分类号： G06F17/50 , G06F30/394 , H01L27/02 , H01L27/118 , H01L23/528 , G06F111/04 , G06F111/20 , G06F119/18
摘要： A method for forming an integrated device includes following operations. A first circuit is provided. The first circuit has a first connecting path, a plurality of second connecting paths, and a third connecting path. The plurality of second connecting paths are electrically connected to a first connecting portion of the first connecting path. The third connecting path is electrically coupled to a second connecting portion of the first connecting path. An electromigration (EM) data of the first connecting path is analyzed to determine if a third connecting portion between the first connecting portion and the second connecting portion induces EM phenomenon. The first circuit is modified for generating a second circuit when the third connecting portion induces EM phenomenon. The integrated device according to the second circuit is generated.
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公开(公告)号：US10515178B2
公开(公告)日：2019-12-24
申请号：US15882188
申请日：2018-01-29
发明人： Hiranmay Biswas , Chung-Hsing Wang , Kuo-Nan Yang , Yi-Kan Cheng
IPC分类号： G06F17/50 , H01L27/02 , H01L27/118
摘要： A method (of generating a layout diagram of a conductive line structure includes: determining that a first set of first to fourth short pillar patterns (which represent portions of an M(i) layer of metallization and are located relative to a grid), violates a minimum transverse-routing (TVR) distance of alpha-direction-separation, wherein (1) the grid has orthogonal alpha and beta tracks, and (2) the short pillar patterns have long axes which are substantially co-track aligned with a first one of the alpha tracks and have a first distance (of alpha-direction-separation between immediately adjacent members of the first set) which is less than the TVR distance; and merging pairings of the first & second and third & fourth short pillar patterns into corresponding first and second medium pillar patterns which have a second distance of alpha-direction-separation therebetween; the second value being greater than the TVR distance.
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39.发明授权公开(公告)号：US10509886B2
公开(公告)日：2019-12-17
申请号：US15844313
申请日：2017-12-15
发明人： Chin-Shen Lin , Meng-Xiang Lee , Kuo-Nan Yang , Chung-Hsing Wang
IPC分类号： G06F17/50
摘要： A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), the layout comprising a resistor-capacitor (RC) netlist comprising a plurality of circuit nodes; identifying an RC network in the RC netlist; determining a characterization matrix corresponding to the RC network; updating the RC netlist by replacing the RC network with the characterization matrix; and calculating voltages and currents of the plurality of circuit nodes based on the updated RC netlist.
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公开(公告)号：US20180047716A1
公开(公告)日：2018-02-15
申请号：US15791320
申请日：2017-10-23
发明人： Chien-Ju Chao , Chou-Kun Lin , Yi-Chuin Tsai , Yen-Hung Lin , Po-Hsiang Huang , Kuo-Nan Yang , Chung-Hsing Wang
IPC分类号： H01L27/02 , H01L23/528 , H01L21/768 , H01L23/50 , H01L21/8234 , H01L27/06
CPC分类号： H01L27/0207 , H01L21/324 , H01L21/768 , H01L21/8221 , H01L21/823475 , H01L21/823871 , H01L23/50 , H01L23/528 , H01L23/5283 , H01L23/5286 , H01L23/53238 , H01L23/5329 , H01L27/0203 , H01L27/0688 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.
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