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公开(公告)号：US12079561B2
公开(公告)日：2024-09-03
申请号：US18362902
申请日：2023-07-31
IPC分类号： G06F30/398 , G03F1/70 , G06F30/392 , G06F30/394
CPC分类号： G06F30/398 , G03F1/70 , G06F30/392 , G06F30/394
摘要： A cell region of a semiconductor device, the cell region including: components (representing a first circuit) including alpha info conductors and dummy conductors which are substantially collinear correspondingly with reference tracks, regarding the first circuit, the alpha info conductors beipng correspondingly for one or more input and/or output signals, or one or more internal signals, and for a majority of the reference tracks, first ends correspondingly of the alpha info conductors or the dummy conductors being aligned and proximal to a first side of the cell region; a first alpha info conductor being on a first reference track and being an intra-cell conductor which does not extend beyond the first side nor a second side of the cell region; and a portion of a first beta info conductor of a second circuit (represented by components of an external cell region) being on the first reference track.
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公开(公告)号：US20240021468A1
公开(公告)日：2024-01-18
申请号：US18446217
申请日：2023-08-08
发明人： Yu-Hsin Chan , Cai-Ling Wu , Chang-Wen Chen , Po-Hsiang Huang , Yu-Yu Chen , Kuan-Wei Huang , Jr-Hung Li , Jay Chiu , Ting-Kui Chang
IPC分类号： H01L21/768 , H01L29/417 , H01L23/522 , H01L23/532
CPC分类号： H01L21/7682 , H01L29/41725 , H01L21/7684 , H01L21/76843 , H01L21/76852 , H01L23/5222 , H01L23/53295 , H01L21/76885 , H01L21/7688 , H01L21/76831 , H01L21/76834
摘要： In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.
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公开(公告)号：US11824254B2
公开(公告)日：2023-11-21
申请号：US17815411
申请日：2022-07-27
发明人： Po-Hsiang Huang , Fong-Yuan Chang , Tsui-Ping Wang , Yi-Shin Chu
CPC分类号： H01Q1/2283 , H01L23/66 , H01Q1/50 , H01Q23/00
摘要： A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.
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公开(公告)号：US11574107B2
公开(公告)日：2023-02-07
申请号：US17339162
申请日：2021-06-04
发明人： Pin-Dai Sue , Po-Hsiang Huang , Fong-Yuan Chang , Chi-Yu Lu , Sheng-Hsiung Chen , Chin-Chou Liu , Lee-Chung Lu , Yen-Hung Lin , Li-Chun Tien , Yi-Kan Cheng
IPC分类号： G06F30/00 , G06F30/392 , G06F30/394 , G06F111/20
摘要： A method of manufacturing a semiconductor device includes forming a transistor layer with an M*1st layer that overlays the transistor layer with one or more first conductors that extend in a first direction. Forming an M*2nd layer that overlays the M*1st layer with one or more second conductors which extend in a second direction. Forming a first pin in the M*2nd layer representing an output pin of a cell region. Forming a long axis of the first pin substantially along a selected one of the one or more second conductors. Forming a majority of the total number of pins in the M*1st layer, the forming including: forming second, third, fourth and fifth pins in the M*1st layer representing corresponding input pins of the circuit; and forming long axes of the second to fifth pins substantially along corresponding ones of the one or more first conductors.
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公开(公告)号：US20220368004A1
公开(公告)日：2022-11-17
申请号：US17815411
申请日：2022-07-27
发明人： Po-Hsiang Huang , Fong-Yuan Chang , Tsui-Ping Wang , Yi-Shin Chu
摘要： A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.
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公开(公告)号：US20220359266A1
公开(公告)日：2022-11-10
申请号：US17873381
申请日：2022-07-26
发明人： Hsiu-Wen Hsueh , Jiing-Feng Yang , Chii-Ping Chen , Po-Hsiang Huang , Chang-Wen Chen , Cai-Ling Wu
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48
摘要： Various embodiments of the present disclosure are directed towards an integrated circuit (IC) in which cavities separate wires of an interconnect structure. For example, a conductive feature overlies a substrate, and an intermetal dielectric (IMD) layer overlies the conductive feature. A first wire and a second wire neighbor in the IMD layer and respectively have a first sidewall and a second sidewall that face each other while being separated from each other by the IMD layer. Further, the first wire overlies and borders the conductive feature. A first cavity and a second cavity further separate the first and second sidewalls from each other. The first cavity separates the first sidewall from the IMD layer, and the second cavity separates the second sidewall from the IMD layer. The cavities reduce parasitic capacitance between the first and second wires and hence resistance-capacitance (RC) delay that degrades IC performance.
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公开(公告)号：US11410929B2
公开(公告)日：2022-08-09
申请号：US16573630
申请日：2019-09-17
发明人： Fong-yuan Chang , Noor Mohamed Ettuveettil , Po-Hsiang Huang , Sen-Bor Jan , Ming-Fa Chen , Chin-Chou Liu , Yi-Kan Cheng
IPC分类号： H01L23/528 , H01L23/522 , H01L23/00
摘要： Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.
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公开(公告)号：US11138362B2
公开(公告)日：2021-10-05
申请号：US17018759
申请日：2020-09-11
IPC分类号： G06F30/398 , H01L27/02 , G03F1/36 , H01L27/118 , G06F30/392 , G06F30/394 , G06F111/04 , G06F119/18
摘要： A method of updating a boundary space configuration of an IC layout cell includes identifying a pin in the IC layout cell as a boundary pin, determining that a boundary spacing of the boundary pin is capable of being increased, and based on the determination that the boundary spacing of the boundary pin is capable of being increased, modifying the IC layout cell by increasing the boundary spacing of the boundary pin. At least one of the identifying, determining, or modifying is executed by a processor of a computer.
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公开(公告)号：US11081426B2
公开(公告)日：2021-08-03
申请号：US16516966
申请日：2019-07-19
IPC分类号： H01L23/48 , H01L25/065 , H01L23/00 , H01L21/822
摘要： A three dimensional Integrated Circuit (IC) Power Grid (PG) may be provided. The three dimensional IC PG may comprise a first IC die, a second IC die, an interface, and a power distribution structure. The interface may be disposed between the first IC die and the second IC die. The power distribution structure may be connected to the interface. The power distribution structure may comprise at least one Through-Silicon Vias (TSV) and a ladder structure connected to at least one TSV.
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公开(公告)号：US11080453B2
公开(公告)日：2021-08-03
申请号：US16599552
申请日：2019-10-11
发明人： Po-Hsiang Huang , Sheng-Hsiung Chen , Chih-Hsin Ko , Fong-Yuan Chang , Clement Hsingjen Wann , Li-Chun Tien , Chia-Ming Hsu
IPC分类号： G11C11/4076 , G11C11/4094 , G11C7/10 , G11C7/12 , G11C7/18 , G11C7/22 , G06F30/392 , H01L27/092 , H01L29/66 , H01L29/78 , H01L21/8238 , G06F30/367 , G06F30/398 , G06F30/3312 , G06F111/20
摘要： A method of operating an IC manufacturing system includes determining whether an n-type active region of a cell or a p-type active region of the cell is a first active region based on a timing critical path of the cell, positioning the first active region along a cell height direction in an IC layout diagram of a cell, the first active region having a first total number of fins extending in a direction perpendicular to the cell height direction. The method also includes positioning a second active region in the cell along the cell height direction, the second active region being the n-type or p-type opposite the n-type or p-type of the first active region and having a second total number of fins less than the first total number of fins and extending in the direction, and storing the IC layout diagram of the cell in a cell library.
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