Integrated circuit and method of forming the same

    公开(公告)号:US12033998B2

    公开(公告)日:2024-07-09

    申请号:US18363230

    申请日:2023-08-01

    IPC分类号: H01L27/02 G06F1/3287

    CPC分类号: H01L27/0207 G06F1/3287

    摘要: An integrated circuit includes a gated circuit configured to operate on at least a first or a second voltage, a header circuit coupled to the gated circuit, a first and second power rail on a back-side of a wafer, and a third power rail on a front-side of the wafer. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The first power rail includes a first portion, a second portion and a third portion, the third portion being between the first portion and the second portion. The second power rail is configured to supply the second voltage to the gated circuit, and is between the first portion and the second portion. The third power rail includes a first set of conductors. Each of the first set of conductors being configured to supply a third voltage to the header circuit.

    Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement

    公开(公告)号:US11347922B2

    公开(公告)日:2022-05-31

    申请号:US17195094

    申请日:2021-03-08

    摘要: A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first conductive layer including segments which are conductive, including forming first segments designated for a first reference voltage and second segments designated for a second reference voltage, and interspersing the first and second segments; relative to a first direction; and forming a second conductive layer over the first conductive layer, the second conductive layer including segments that are conductive, including forming third segments designated for the first reference voltage and fourth segments designated for the second reference voltage, interspersing the third and fourth segments relative to a second direction, the second direction being perpendicular to the first direction, and arranging the segments in the second conductive layer substantially asymmetrically including, relative to the first direction, locating each fourth segment substantially asymmetrically between corresponding adjacent ones of the third segments.

    Via sizing for IR drop reduction
    6.
    发明授权

    公开(公告)号:US11211327B2

    公开(公告)日:2021-12-28

    申请号:US16731719

    申请日:2019-12-31

    摘要: A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.

    Cell having shifted boundary and boundary-shift scheme
    10.
    发明授权
    Cell having shifted boundary and boundary-shift scheme 有权
    移位边界和边界移位方案

    公开(公告)号:US09262573B2

    公开(公告)日:2016-02-16

    申请号:US13791406

    申请日:2013-03-08

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5072 G06F17/5081

    摘要: An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.

    摘要翻译: 实施例小区移位方案包括将第一晶体管单元抵靠第二晶体管单元并将位置和布线边界移离设置在第一晶体管单元和第二晶体管单元之间的多晶硅。 在一个实施例中,小区移位方案包括移动位置和路由边界以防止布局与示意图(LVS)网表和后仿真网表之间的不匹配。