公开(公告)号：US11115383B2

公开(公告)日：2021-09-07

申请号：US16221318

申请日：2018-12-14

Applicant: Texas Instruments Incorporated

Inventor： Amritpal Singh Mundra ,  Chunhua Hu

IPC: H04L29/06

Abstract: In described examples, a system on a chip (SoC) and method for sending messages in the SoC include determining locations of initiator-side firewall block and receiver-side firewall block memories using respective pointers to the firewall block memories stored in a single, contiguous memory. Addresses of the pointers within the single memory depend on respective unique firewall identifiers of the firewall blocks. An exclusive security configuration controller uses the pointers to configure the firewall blocks over a security bus which is electrically isolated from a system bus. The system bus is used to send messages from sending functional blocks to receiving functional blocks. The initiator-side firewall block adds a message identifier to messages. The message identifier depends on the initiator-side firewall block's configuration settings. The receiver-side firewall block controls permission for the receiving functional block to access the message, depending on the message identifier and the receiver-side firewall block's configuration settings.

公开(公告)号：US20210044292A1

公开(公告)日：2021-02-11

申请号：US17080239

申请日：2020-10-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua Hu ,  Venkateswar Reddy Kowkutla ,  Charles Fuoco

IPC: H03K17/22

Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.

公开(公告)号：US10402355B2

公开(公告)日：2019-09-03

申请号：US15890558

申请日：2018-02-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Brian Karguth ,  Chuck Fuoco ,  Chunhua Hu ,  Todd Christopher Hiers

IPC: G06F13/28 ,  G06F12/1081 ,  G06F13/42

Abstract: An address space field is used in conjunction with a normal address field to allow indication of an address space for the particular address value. In one instance, one address space value is used to indicate the bypassing of the address translation used between address spaces. A different address space value is designated for conventional operation, where address translations are performed. Other address space values are used to designate different transformations of the address values or the data. This technique provides a simplified format for handling address values and the like between different devices having different address spaces, simplifying overall computer system design and operation.

公开(公告)号：US20190212794A1

公开(公告)日：2019-07-11

申请号：US16299544

申请日：2019-03-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua Hu ,  Venkateswar Reddy Kowkutla ,  Charles Fuoco

IPC: G06F1/24 ,  G06F1/28 ,  G06F11/22

CPC classification number: G06F1/24 ,  G06F1/28 ,  G06F11/22

Abstract: Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.

公开(公告)号：US10228736B2

公开(公告)日：2019-03-12

申请号：US15395156

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chunhua Hu ,  Venkateswar Reddy Kowkutla ,  Charles Fuoco

IPC: G06F1/24

Abstract: The reset isolation mechanism describes an embedded safety island inside a system on a chip which reduces the overall system cost while achieving functional safety. The safety island ensures an orderly shutdown of all or part of the rest of the system on a chip without the possibility of a safety island hang due to incomplete transactions at the time of the reset.

公开(公告)号：US10050617B2

公开(公告)日：2018-08-14

申请号：US15387683

申请日：2016-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Venkateswar Reddy Kowkutla ,  Erkan Bilhan ,  Sumant Dinkar Kale ,  Chunhua Hu

IPC: H03K17/22 ,  H03B5/32

CPC classification number: H03K17/22 ,  H03B5/32

Abstract: A functional safety Power on Reset system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. A plurality of voltage monitoring stages is implemented to ensure redundancy.