公开(公告)号：US12175244B2

公开(公告)日：2024-12-24

申请号：US18507222

申请日：2023-11-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L. Davis

IPC: G06F9/30

Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

公开(公告)号：US20240320004A1

公开(公告)日：2024-09-26

申请号：US18670855

申请日：2024-05-22

Applicant: Texas Instruments Incorporated

Inventor： Duc Bui ,  Peter Richard Dent ,  Timothy D. Anderson

IPC: G06F9/30

CPC classification number: G06F9/3013 ,  G06F9/30036 ,  G06F9/30105

Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.

公开(公告)号：US12032961B2

公开(公告)日：2024-07-09

申请号：US18191066

申请日：2023-03-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Bui ,  Peter Richard Dent ,  Timothy D. Anderson

IPC: G06F9/30

CPC classification number: G06F9/3013 ,  G06F9/30036 ,  G06F9/30105

Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.

公开(公告)号：US20240036866A1

公开(公告)日：2024-02-01

申请号：US18355939

申请日：2023-07-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Bui ,  Timothy D. Anderson ,  Paul Gauvreau

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3802 ,  G06F9/3836

Abstract: Disclosed herein are systems and methods for executing multiple instruction set architectures (ISAs) on a singular processing unit. In an implementation, a processor that includes a first decoder, a second decoder, instruction fetch circuitry, and instruction dispatch circuitry is configured to execute two separate instruction set architectures. In an implementation, the instruction fetch circuitry is configured to fetch instructions from an associated memory. In an implementation the instruction dispatch circuitry is coupled to the instruction fetch circuitry, the first decoder, and the second decoder and is configured to route instructions associated with a first ISA to the first decoder, and route instructions associated with a second ISA to the second decoder.

公开(公告)号：US20230367598A1

公开(公告)日：2023-11-16

申请号：US18191066

申请日：2023-03-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Bui ,  Peter Richard Dent ,  Timothy D. Anderson

IPC: G06F9/30

CPC classification number: G06F9/3013 ,  G06F9/30105 ,  G06F9/30036

Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.

公开(公告)号：US11816485B2

公开(公告)日：2023-11-14

申请号：US17367384

申请日：2021-07-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai Chirca ,  Timothy D. Anderson ,  Todd T. Hahn ,  Alan L. Davis

IPC: G06F9/30

CPC classification number: G06F9/30065 ,  G06F9/3013

Abstract: A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

公开(公告)号：US11789742B2

公开(公告)日：2023-10-17

申请号：US17688260

申请日：2022-03-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Duc Bui ,  Joseph Zbiciak ,  Reid E. Tatge

IPC: G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/3838

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

公开(公告)号：US11501024B2

公开(公告)日：2022-11-15

申请号：US16047298

申请日：2018-07-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Joseph R. M. Zbiciak ,  Matthew D. Pierson ,  Kai Chirca

IPC: G06F21/78 ,  G06F12/0815 ,  G06F21/79 ,  G06F12/14 ,  G06F12/0817 ,  G06F13/16 ,  G06F13/30 ,  G06F12/0831 ,  H04L9/40 ,  G06F13/42 ,  G06F12/1081 ,  G06F13/28 ,  G06F13/40 ,  G06F12/0842

Abstract: Disclosed embodiments relate to a security firewall having a security hierarchy including: secure master (SM); secure guest (SG); and non-secure (NS). There is one secure master and n secure guests. The firewall includes one secure region for secure master and one secure region for secure guests. The SM region only allows access from the secure master and the SG region allows accesses from any secure transaction. Finally, the non-secure region can be implemented two ways. In a first option, non-secure regions may be accessed only upon non-secure transactions. In a second option, non-secure regions may be accessed any processing core. In this second option, the access is downgraded to a non-secure access if the security identity is secure master or secure guest. If the two security levels are not needed the secure master can unlock the SM region to allow any secure guest access to the SM region.

公开(公告)号：US20220214878A1

公开(公告)日：2022-07-07

申请号：US17705453

申请日：2022-03-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Duc Bui

IPC: G06F9/30

Abstract: A method to reverse source data in a processor in response to a vector reverse instruction includes specifying, in respective fields of the vector reverse instruction, a source register containing the source data and a destination register. The source register includes a plurality of lanes and each lane contains a data element, and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector reverse instruction by creating reversed source data by reversing the order of the data elements, and storing the reversed source data in the destination register.

公开(公告)号：US11269650B2

公开(公告)日：2022-03-08

申请号：US16685747

申请日：2019-11-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy D. Anderson ,  Duc Bui ,  Joseph Zbiciak ,  Reid E. Tatge

IPC: G06F9/38

Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.