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    Alternating frame processing operation with predicted frame comparisons for high safety level use
    31.
    发明授权
    Alternating frame processing operation with predicted frame comparisons for high safety level use 有权

    公开(公告)号：US11895326B2

    公开(公告)日：2024-02-06

    申请号：US18079237

    申请日：2022-12-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Aishwarya Dubey ,  Shashank Dabral ,  Veeramanikandan Raju

    IPC: H04N19/557 ,  H04N19/577 ,  H04N19/567 ,  G01S17/89 ,  G01S17/86

    CPC classification number: H04N19/557 ,  G01S17/86 ,  G01S17/89 ,  H04N19/567 ,  H04N19/577

    Abstract: Frames from an image stream or streams are processed by independently operating digital signal processors (DSPs), with only frame checking microprocessors operating in a lockstep mode. In one example, two DSP are operating on alternate frames. Each DSP processes the frames and produces prediction values for the next frame. The lockstep microprocessors develop their own next frame prediction. The lockstep processors compare issued frames and previously developed predicted frames for consistency. If the predictions are close enough, the issued frame passes the test. The lockstep processors then compare the issued frame to the preceding two frames for a similar consistency check. If the prior frames are also close enough, the issued frame is acceptable. In another example, hardware checkers are provided to compare the present frame with a larger number of prior frames. The hardware checkers provide comparison results to the lockstep processors to compare against allowable variation limits.

    Fault detection within an analog-to-digital converter
    33.
    发明授权
    Fault detection within an analog-to-digital converter 有权

    公开(公告)号：US11606099B1

    公开(公告)日：2023-03-14

    申请号：US17482734

    申请日：2021-09-23

    Applicant: Texas Instruments Incorporated

    Inventor： Veeramanikandan Raju ,  Anand Kumar G

    IPC: H03M1/06

    Abstract: An integrated circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs and a digital output. A window comparator coupled to the digital output. The window comparator configured to compare a digital value on the digital output to first and second threshold values. A programmable clock circuit configured to provide a clock signal to the ADC. A controller that, response to assertion of the trigger signal, is configured to generate a sample rate control signal to the clock circuit to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs. A result comparison circuit having a comparison input coupled to the digital output. The result comparison circuit is configured to compare a first digital conversion output from the ADC to a second digital conversion output from the ADC.

    Machine learning model with watermarked weights
    36.
    发明授权
    Machine learning model with watermarked weights 有权

    公开(公告)号：US11163861B2

    公开(公告)日：2021-11-02

    申请号：US16188560

    申请日：2018-11-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Deepak Kumar Poddar ,  Mihir Mody ,  Veeramanikandan Raju ,  Jason A. T. Jones

    IPC: G06F21/00 ,  G06F21/16 ,  G06N3/04 ,  G06N20/00 ,  G06F21/12

    Abstract: In some examples, a system includes storage storing a machine learning model, wherein the machine learning model comprises a plurality of layers comprising multiple weights. The system also includes a processing unit coupled to the storage and operable to group the weights in each layer into a plurality of partitions; determine a number of least significant bits to be used for watermarking in each of the plurality of partitions; insert one or more watermark bits into the determined least significant bits for each of the plurality of partitions; and scramble one or more of the weight bits to produce watermarked and scrambled weights. The system also includes an output device to provide the watermarked and scrambled weights to another device.

    Dynamic security protection in configurable analog signal chains
    37.
    发明授权
    Dynamic security protection in configurable analog signal chains 有权

    公开(公告)号：US10935600B2

    公开(公告)日：2021-03-02

    申请号：US16376697

    申请日：2019-04-05

    Applicant: Texas Instruments Incorporated

    Inventor： Veeramanikandan Raju ,  Anand Kumar G ,  Christy Leigh She

    IPC: G01R31/3185 ,  G06F21/45 ,  G06F21/31 ,  H04L29/06

    Abstract: A system and method for dynamically protecting against security vulnerabilities in a reconfigurable signal chain. The system includes a signal chain formed from at least a first component connected with a second component. The first component has a set of source outputs and a first authentication block, and the second signal chain component has a set of destination inputs and a second authentication block. The system also includes a signal chain configurator that populates the first authentication block with at least one validated endpoint from the set of destination inputs. A signal chain integrity block, which is communicatively coupled with the first authentication block and the second authentication block, identifies a source-destination pair from one or more endpoint pairs formed from the at least one validated endpoint and the set of source outputs. The signal chain integrity block propagates the source-destination pair to the first authentication block and the second authentication block. The second authentication block authenticates any received input using the source-destination pair.

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