公开(公告)号：US20190035646A1

公开(公告)日：2019-01-31

申请号：US16047711

申请日：2018-07-27

Applicant: Tokyo Electron Limited

Inventor： Ronald Nasman ,  Gerrit J. Leusink ,  Rodney L. Robison ,  Hoyoung Kang ,  Daniel Fulford

IPC: H01L21/67 ,  C23C16/455 ,  C23C16/52

Abstract: Techniques herein include a process chamber for depositing thin films to backside surfaces of wafers to reduce wafer bowing and distortion. A substrate support provides an annular perimeter seal around the bottom and/or side of the wafer which allows the majority of the substrate backside to be exposed to a process environment. A supported wafer separates the chamber into lower and upper chambers that provide different process environments. The lower section of the processing chamber includes deposition hardware configured to apply and remove thin films. The upper section can remain a chemically inert environment, protecting the existing features on the top surface of the wafer. Multiple exhausts and differential pressures are used to prevent deposition gasses from accessing the working surface of a wafer.

公开(公告)号：US20190033711A1

公开(公告)日：2019-01-31

申请号：US16046272

申请日：2018-07-26

Applicant: Tokyo Electron Limited

Inventor： Hoyoung Kang

IPC: G03F7/00

Abstract: Methods and systems for imprint lithography are described. In an embodiment, a method may include receiving a substrate in an imprint lithography chamber. Such a method may also include applying a deformable layer to a surface of the substrate. The method may further include injecting a gas that dissolves into the deformable layer more quickly than air into the chamber. Additionally, the method may include pressing a mold into the deformable layer. The method may also include controlling one or more processing parameters in order to achieve device formation objectives.

公开(公告)号：US09385129B2

公开(公告)日：2016-07-05

申请号：US14720279

申请日：2015-05-22

Applicant: Tokyo Electron Limited

Inventor： Hoyoung Kang

IPC: H01L21/00 ,  H01L27/108 ,  H01L21/311 ,  H01L21/768 ,  H01L21/31 ,  H01L21/283 ,  H01L23/532 ,  H01L49/02 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/31116 ,  H01L21/31 ,  H01L21/31138 ,  H01L21/31144 ,  H01L27/10852 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor structure and method of forming thereof on a substrate is described. The capacitor structure includes a substrate having a plurality of capacitor electrodes formed within an insulative retaining material, and a collar layer structure in contact with the plurality of capacitor electrodes, wherein the collar layer structure interconnects the plurality of capacitor electrodes and exposes the underlying insulative retaining material through openings having an unguided, random self-assembly pattern. Furthermore, the insulative retaining material may be removed from the capacitor structure. The method includes using a self-assembly process to form the interconnecting collar layer structure.

Abstract translation: 描述了一种电容器结构及其在衬底上的形成方法。 电容器结构包括具有形成在绝缘保持材料内的多个电容器电极的基板和与所述多个电容器电极接触的轴环层结构，其中所述轴环层结构将所述多个电容器电极互连并且暴露所述下面的绝缘保持 材料通过开口具有非导向的随机自组装图案。 此外，绝缘保持材料可以从电容器结构移除。 该方法包括使用自组装工艺来形成互连套环层结构。

公开(公告)号：US20160148812A1

公开(公告)日：2016-05-26

申请号：US14676356

申请日：2015-04-01

Applicant: Tokyo Electron Limited

Inventor： Hoyoung Kang

IPC: H01L21/304 ,  H01L21/324 ,  H05B3/22 ,  H01L21/311 ,  H01L21/67 ,  H01L21/027 ,  H01L21/683

CPC classification number: H01L21/304 ,  H01L21/0273 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/67109 ,  H01L21/67748 ,  H01L21/68735 ,  H05B3/22

Abstract: Provided is a method for processing a semiconductor substrate to reduce line roughness, the method comprising: positioning a substrate in a film-forming system, the film-forming system comprising a chuck having a clamping mechanism configured to hold the substrate in a processing chamber and flex the substrate by displacing a center of the substrate relative to a peripheral edge of the substrate so as to create a concave surface during processing; coating the substrate with a layer of material; performing a post apply bake process; flexing the substrate to create the concave surface either during the post apply bake or following the post apply bake process, wherein the concave surface has a degree of concavity measured at the center of the substrate that exceeds a base number of microns; and unflexing the substrate and inducing tensile stress in the layer of material on the substrate.

Abstract translation: 提供了一种处理半导体衬底以减少线粗糙度的方法，所述方法包括：将衬底定位在成膜系统中，所述成膜系统包括具有夹持机构的卡盘，所述夹持机构构造成将衬底保持在处理室中， 通过相对于衬底的周边移位衬底的中心来弯曲衬底，以便在加工过程中产生凹面; 用一层材料涂覆基材; 执行贴子烘焙过程; 在施加后烘烤或后施加烘烤过程期间使衬底弯曲以形成凹面，其中凹面具有在衬底的中心处测量的超过基数微米的凹度; 并且使衬底不折叠并且在衬底上的材料层中引起拉伸应力。