公开(公告)号：US20190148551A1

公开(公告)日：2019-05-16

申请号：US15997130

申请日：2018-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Shahaji B. MORE ,  Huai-Tei Yang ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/167 ,  H01L29/165 ,  H01L21/02 ,  H01L21/8238

Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.

公开(公告)号：US10164100B2

公开(公告)日：2018-12-25

申请号：US16004727

申请日：2018-06-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shahaji B. More ,  Zheng-Yang Pan ,  Chun-Chieh Wang ,  Cheng-Han Lee ,  Shih-Chieh Chang

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/267 ,  H01L29/36 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/165

Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain structure near the gate structure. The source/drain structure has an inner portion and an outer portion surrounding an entirety of the inner portion. The inner portion has a greater average dopant concentration than that of the outer portion.

公开(公告)号：US10043665B2

公开(公告)日：2018-08-07

申请号：US15399143

申请日：2017-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Zheng-Yang Pan ,  Cheng-Han Lee ,  Shih-Chieh Chang ,  Chandrashekhar Prakash Savant

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/41 ,  H01L29/786 ,  H01L29/10 ,  H01L29/66

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a first source portion and a first drain portion over the substrate, and a first semiconductor nanowire over the substrate and between the first source portion and the first drain portion. The first semiconductor nanowire includes a first portion over the substrate and a second portion over the first portion, and the first portion has a first width, and the second portion has a second width, and the second width is less than the first width. The semiconductor device structure also includes a first gate structure over the second portion of the first semiconductor nanowire.

公开(公告)号：US20240395937A1

公开(公告)日：2024-11-28

申请号：US18791144

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Min Huang ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66

Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.

公开(公告)号：US11469305B2

公开(公告)日：2022-10-11

申请号：US16935890

申请日：2020-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Cheng-Han Lee

IPC: H01L29/417 ,  H01L29/04 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, and a source/drain (S/D) region adjacent to the gate structure. The S/D region can include first and second side surfaces separated from each other. The S/D region can further include top and bottom surfaces between the first and second side surfaces. A first separation between the top and bottom surfaces can be greater than a second separation between the first and second side surfaces.

公开(公告)号：US11444199B2

公开(公告)日：2022-09-13

申请号：US16984075

申请日：2020-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shahaji B. More ,  Shih-Chieh Chang ,  Cheng-Han Lee ,  Pei-Shan Lee

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/786 ,  H01L29/423

Abstract: A semiconductor device includes semiconductor wires or sheets disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires or sheets, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires or sheets, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor wires or sheets, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.

公开(公告)号：US20200152742A1

公开(公告)日：2020-05-14

申请号：US16741607

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Huai-Tei YANG ,  Zheng-Yang PAN ,  Shih-Chieh CHANG ,  Chun-Chieh WANG ,  Cheng-Han Lee

IPC: H01L29/10 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/74 ,  H01L29/78 ,  H01L29/66

Abstract: The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF3) and ammonia (NH3) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof.

公开(公告)号：US12249650B2

公开(公告)日：2025-03-11

申请号：US18185602

申请日：2023-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang

IPC: H01L29/08 ,  H01L21/225 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/161 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a substrate; a fin protruding above the substrate, the fin including a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, where a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate; a gate structure over the fin; a channel region in the fin and directly under the gate structure; and source/drain regions on opposing sides of the gate structure, the source/drain regions including a second dopant, where a concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, where the concentration of the first dopant at the first location is lower than that at the second location.

公开(公告)号：US12142681B2

公开(公告)日：2024-11-12

申请号：US17379569

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Min Huang ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66

Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.

公开(公告)号：US20240304724A1

公开(公告)日：2024-09-12

申请号：US18662615

申请日：2024-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. MORE ,  Huai-Tei Yang ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/167 ,  H01L29/66803 ,  H01L29/161 ,  H01L29/165

Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.