公开(公告)号：US20240379853A1

公开(公告)日：2024-11-14

申请号：US18782106

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Shih-Chieh Chang

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49

Abstract: A FinFET device and a method of forming the same are provided. The method includes forming semiconductor strips over a substrate. Isolation regions are formed over the substrate and between adjacent semiconductor strips. A first recess process is performed on the isolation regions to expose first portions of the semiconductor strips. The first portions of the semiconductor strips are reshaped to form reshaped first portions of the semiconductor strips. A second recess process is performed on the isolation regions to expose second portions of the semiconductor strips below the reshaped first portions of the semiconductor strips. The second portions of the semiconductor strips are reshaped to form reshaped second portions of the semiconductor strips. The reshaped first portions of the semiconductor strips and the reshaped second portions of the semiconductor strips form fins. The fins extend away from topmost surfaces of the isolation regions.

公开(公告)号：US12142663B2

公开(公告)日：2024-11-12

申请号：US18357823

申请日：2023-07-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shahaji B. More ,  Chun Hsiung Tsai ,  Shih-Chieh Chang ,  Kuo-Feng Yu ,  Cheng-Yi Peng

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/311 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/161

Abstract: A semiconductor structure includes a substrate, a semiconductor fin extending from the substrate, and a silicon germanium (SiGe) epitaxial feature disposed over the semiconductor fin. A gallium-implanted layer is disposed over a top surface of the SiGe epitaxial feature, and a silicide feature is disposed over and in contact with the gallium-implanted layer.

公开(公告)号：US12080761B2

公开(公告)日：2024-09-03

申请号：US17582727

申请日：2022-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Huai-Tei Yang ,  Zheng-Yang Pan ,  Shih-Chieh Chang ,  Chun-Chieh Wang ,  Cheng-Han Lee

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/74 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1054 ,  H01L21/02057 ,  H01L21/02645 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/74 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7851 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02661

Abstract: The present disclosure describes an exemplary fin structure formed on a substrate. The disclosed fin structure comprises an n-type doped region formed on a top portion of the substrate, a silicon epitaxial layer on the n-type doped region, and an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer. The fin structure can further comprise a liner surrounding the n-type doped region, and a dielectric surrounding the liner.

公开(公告)号：US11854811B2

公开(公告)日：2023-12-26

申请号：US17230660

申请日：2021-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Min Huang ,  Huai-Tei Yang ,  Shih-Chieh Chang

IPC: H01L21/285 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L23/485

CPC classification number: H01L21/28518 ,  H01L21/02532 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/7851 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823814 ,  H01L23/485

Abstract: A finFET device and methods of forming are provided. The method includes etching recesses in a substrate on opposite sides of a gate stack. The method also includes epitaxially growing a source/drain region in each recess, where each of the source/drain regions includes a capping layer along a top surface of the respective source/drain region, and where a concentration of a first material in each source/drain region is highest at an interface of the capping layer and an underlying epitaxy layer. The method also includes depositing a plurality of metal layers overlying and contacting each of the source/drain regions. The method also includes performing an anneal, where after the anneal a metal silicide region is formed in each of the source/drain regions, where each metal silicide region extends through the capping layer and terminates at the interface of the capping layer and the underlying epitaxy layer.

公开(公告)号：US20230377991A1

公开(公告)日：2023-11-23

申请号：US18366763

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Lin ,  Kun-Yu Lee ,  Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang

IPC: H01L21/8238 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.

公开(公告)号：US11817492B2

公开(公告)日：2023-11-14

申请号：US17554961

申请日：2021-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Shih-Chieh Chang

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/04 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02603 ,  H01L21/0455 ,  H01L21/823431 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/7856 ,  H01L2029/7858

Abstract: Methods are disclosed for forming a multi-layer structure including highly controlled diffusion interfaces between alternating layers of different semiconductor materials. According to embodiments, during a deposition of semiconductor layers, the process is controlled to remain at low temperatures such that an inter-diffusion rate between the materials of the deposited layers is managed to provide diffusion interfaces with abrupt Si/SiGe interfaces. The highly controlled interfaces and first and second layers provide a multi-layer structure with improved etching selectivity. In an embodiment, a gate all-around (GAA) transistor is formed with horizontal nanowires (NWs) from the multi-layer structure with improved etching selectivity. In embodiments, horizontal NWs of a GAA transistor may be formed with substantially the same size diameters and silicon germanium (SiGe) NWs may be formed with “all-in-one” silicon (Si) caps.

公开(公告)号：US11776851B2

公开(公告)日：2023-10-03

申请号：US17734521

申请日：2022-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Ma ,  Zheng-Yang Pan ,  Shahaji B. More ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L21/823418 ,  H01L21/0245 ,  H01L21/0262 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53257 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66348 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7848 ,  H01L21/02576 ,  H01L21/02579 ,  H01L29/165

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.

公开(公告)号：US20230154802A1

公开(公告)日：2023-05-18

申请号：US18149495

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Han Lee ,  Chih-Yu Ma ,  Shih-Chieh Chang

IPC: H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/0243 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/7849 ,  H01L29/7851

Abstract: A structure includes a stepped crystalline substrate that includes an upper step, a lower step, and a step rise. A first fin includes a crystalline structure having a first lattice constant. The first fin is formed over the lower step. A second fin includes a crystalline structure having a second lattice constant, the second lattice constant being different than the first lattice constant. The second fin can be formed over the upper step apart from the first fin. A second crystalline structure can be formed over the first crystalline structure and the tops of the fins aligned. The first and second fins can be made of the same material, but with different heights and different channel strain values. The first fin can be used as an NMOS fin and the second fin can be used as a PMOS fin of a CMOS FinFET.

公开(公告)号：US20230102873A1

公开(公告)日：2023-03-30

申请号：US18061031

申请日：2022-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Ma ,  Shahaji B. More ,  Yi-Min Huang ,  Shih-Chieh Chang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.

公开(公告)号：US20220149176A1

公开(公告)日：2022-05-12

申请号：US17226905

申请日：2021-04-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Cheng-Han Lee ,  Shih-Chieh Chang

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: A device includes a first gate region having a first gate length; a first spacer on a sidewall of the first gate region; a semiconductor layer over the first gate region; a second gate region over the semiconductor layer, wherein the second gate region has a second gate length equal to the first gate length; and a second spacer on a sidewall of second gate region, wherein the second spacer is wider than the first spacer.