公开(公告)号：US20180130802A1

公开(公告)日：2018-05-10

申请号：US15348652

申请日：2016-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh WANG ,  Zheng-Yang PAN ,  Yi-Min HUANG ,  Shih-Chieh CHANG ,  Tsung-Lin LEE

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/0928 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/7851

Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure extending above a substrate, and the fin structure has a first portion and a second portion below the first portion, and the first portion and the second portion are made of different materials. The FinFET device structure includes an isolation structure formed on the substrate, and an interface between the first portion and the second portion of the fin structure is above a top surface of the isolation structure. The FinFET device structure includes a liner layer formed on sidewalls of the second portion of the fin structure.

公开(公告)号：US20190164822A1

公开(公告)日：2019-05-30

申请号：US15887819

申请日：2018-02-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tien-Pei CHOU ,  Ken-Yu CHANG ,  Chun-Chieh WANG ,  Yueh-Ching PAI ,  Yu-Ting LIN ,  Yu-Wen CHENG

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L29/78 ,  H01L23/522

CPC classification number: H01L21/76846 ,  C23C16/02 ,  C23C16/0209 ,  C23C16/0227 ,  C23C16/45536 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/823431 ,  H01L23/5226 ,  H01L23/53209 ,  H01L29/41791 ,  H01L29/785 ,  H01L2029/7858

Abstract: The present disclosure relates generally to techniques for forming a continuous adhesion layer for a contact plug. A method includes forming an opening through a dielectric layer to an active area on a substrate. The method includes performing a first plasma treatment along a sidewall of the opening. The method includes performing an atomic layer deposition (ALD) process to form a metal nitride layer along the sidewall of the opening. The ALD process includes a plurality of cycles. Each cycle includes flowing a precursor to form a metal monolayer along the sidewall and performing a second plasma treatment to treat the metal monolayer with nitrogen. The method includes depositing a conductive material on the metal nitride layer in the opening to form a conductive feature.

公开(公告)号：US20180108775A1

公开(公告)日：2018-04-19

申请号：US15292428

申请日：2016-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. MORE ,  Zheng-Yang PAN ,  Chun-Chieh WANG ,  Cheng-Han LEE ,  Shih-Chieh CHANG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/267 ,  H01L29/36 ,  H01L29/417 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/267 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/66636

Abstract: Structures of a semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, and a first recess and a second recess in the substrate and at opposite sides of the gate structure. The semiconductor device also includes two source/drain structures over the first recess and the second recess respectively. At least one of the source/drain structures includes a first doped region partially filling in the first recess, a second doped region over the first doped region, and a third doped region over the second doped region. The second doped region contains more dopants than the first doped region or the third doped region.

公开(公告)号：US20220149157A1

公开(公告)日：2022-05-12

申请号：US17582727

申请日：2022-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. MORE ,  Huai-Tei YANG ,  Zheng-Yang PAN ,  Shih-Chieh CHANG ,  Chun-Chieh WANG ,  Cheng-Han LEE

IPC: H01L29/10 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/74 ,  H01L21/308 ,  H01L27/092 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/06

Abstract: The present disclosure describes an exemplary fin structure formed on a substrate. The disclosed fin structure comprises an n-type doped region formed on a top portion of the substrate, a silicon epitaxial layer on the n-type doped region, and an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer. The fin structure can further comprise a liner surrounding the n-type doped region, and a dielectric surrounding the liner.

公开(公告)号：US20190148556A1

公开(公告)日：2019-05-16

申请号：US16043371

申请日：2018-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh WANG ,  Yu-Ting LIN ,  Yueh-Ching PAI ,  Shih-Chieh CHANG ,  Huai-Tei YANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/3065 ,  H01L27/088

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer and a source/drain structure. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The source/drain structure includes a first source/drain epitaxial layer and a second source/drain epitaxial layer. The first source/drain epitaxial layer is in contact with the fin structure. The first source/drain epitaxial layer is connected to a portion of the second source/drain epitaxial layer below a top surface of the fin structure. The lattice constant of the first source/drain epitaxial layer is different from the lattice constant of the second source/drain epitaxial layer.

公开(公告)号：US20200243683A1

公开(公告)日：2020-07-30

申请号：US16851728

申请日：2020-04-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shahaji B. MORE ,  Zheng-Yang PAN ,  Chun-Chieh WANG ,  Cheng-Han LEE ,  Shih-Chieh CHANG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/267 ,  H01L29/36 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/165 ,  H01L29/417

Abstract: A method for forming a semiconductor device is provided. The method includes forming a gate stack to partially cover a semiconductor structure. The method also includes forming a first semiconductor material over the semiconductor structure. The method further includes forming a second semiconductor material over the first semiconductor material. In addition, the method includes forming a third semiconductor material over the second semiconductor material. The first semiconductor material and the third semiconductor material together surround the second semiconductor material. The second semiconductor material has a greater dopant concentration than that of the first semiconductor material or that of the third semiconductor material.

公开(公告)号：US20200152742A1

公开(公告)日：2020-05-14

申请号：US16741607

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Huai-Tei YANG ,  Zheng-Yang PAN ,  Shih-Chieh CHANG ,  Chun-Chieh WANG ,  Cheng-Han Lee

IPC: H01L29/10 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/74 ,  H01L29/78 ,  H01L29/66

Abstract: The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF3) and ammonia (NH3) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof.

公开(公告)号：US20190096997A1

公开(公告)日：2019-03-28

申请号：US15719046

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. MORE ,  Huai-Tei YANG ,  Zheng-Yang PAN ,  Shih-Chieh CHANG ,  Chun-Chieh WANG ,  Cheng-Han LEE

IPC: H01L29/10 ,  H01L21/8238 ,  H01L21/74 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092 ,  H01L29/06

Abstract: The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF3) and ammonia (NH3) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof.

公开(公告)号：US20180145076A1

公开(公告)日：2018-05-24

申请号：US15356004

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh WANG ,  Zheng-Yang PAN ,  Shih-Chieh CHANG ,  Yi-Min HUANG ,  Shahaji B. MORE ,  Tsung-Lin LEE

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66

Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure extending above a substrate. The fin structure includes a channel region, a portion of the channel region is made of silicon germanium (SiGe), and the silicon germanium (SiGe) has a gradient germanium (Ge) concentration. The FinFET device structure includes a gate structure formed on the channel region of the fin structure.

公开(公告)号：US20210202327A1

公开(公告)日：2021-07-01

申请号：US16937732

申请日：2020-07-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh WANG ,  Yueh-Ching PAI

IPC: H01L21/8238 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66

Abstract: In a method of manufacturing a semiconductor device, semiconductor layers, which are vertically arranged with a space between adjacent semiconductor layers, are provided over a substrate, an interfacial layer is formed around each of the semiconductor layers, a dielectric layer is formed on the interfacial layer around each of the semiconductor layers, a first conductive layer is formed on the dielectric layer, the first conductive layer is removed so that the dielectric layer is exposed, a second conductive layer is formed on the exposed dielectric layer so that the space between adjacent semiconductor layers is not fully filled by the second conductive layer, a third conductive layer is formed on the second conductive layer so that the space between adjacent semiconductor layers is filled by the third conductive layer, and the semiconductor layers are semiconductor wires or sheets.