公开(公告)号：US12266573B2

公开(公告)日：2025-04-01

申请号：US17483043

申请日：2021-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi Chen Ho ,  Yiting Chang ,  Chi-Hsun Lin ,  Zheng-Yang Pan

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/762 ,  H01L27/088

Abstract: In an embodiment, a device includes: an isolation region on a substrate; a first semiconductor fin protruding above the isolation region; a second semiconductor fin protruding above the isolation region; and a dielectric fin between the first semiconductor fin and the second semiconductor fin, the dielectric fin protruding above the isolation region, the dielectric fin including: a first layer including a first dielectric material having a first carbon concentration; and a second layer on the first layer, the second layer including a second dielectric material having a second carbon concentration, the second carbon concentration greater than the first carbon concentration.

公开(公告)号：US11342228B2

公开(公告)日：2022-05-24

申请号：US16983527

申请日：2020-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Ma ,  Zheng-Yang Pan ,  Shahaji B. More ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/485 ,  H01L29/08 ,  H01L29/165

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.

公开(公告)号：US10164100B2

公开(公告)日：2018-12-25

申请号：US16004727

申请日：2018-06-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shahaji B. More ,  Zheng-Yang Pan ,  Chun-Chieh Wang ,  Cheng-Han Lee ,  Shih-Chieh Chang

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/267 ,  H01L29/36 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/165

Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain structure near the gate structure. The source/drain structure has an inner portion and an outer portion surrounding an entirety of the inner portion. The inner portion has a greater average dopant concentration than that of the outer portion.

公开(公告)号：US10043665B2

公开(公告)日：2018-08-07

申请号：US15399143

申请日：2017-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Zheng-Yang Pan ,  Cheng-Han Lee ,  Shih-Chieh Chang ,  Chandrashekhar Prakash Savant

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/41 ,  H01L29/786 ,  H01L29/10 ,  H01L29/66

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a first source portion and a first drain portion over the substrate, and a first semiconductor nanowire over the substrate and between the first source portion and the first drain portion. The first semiconductor nanowire includes a first portion over the substrate and a second portion over the first portion, and the first portion has a first width, and the second portion has a second width, and the second width is less than the first width. The semiconductor device structure also includes a first gate structure over the second portion of the first semiconductor nanowire.

公开(公告)号：US09899273B1

公开(公告)日：2018-02-20

申请号：US15379983

申请日：2016-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Wang ,  Yi-Min Huang ,  Huai-Tei Yang ,  Shih-Chieh Chang ,  Zheng-Yang Pan

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/265

CPC classification number: H01L21/823892 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/82385 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/0928

Abstract: Semiconductor structures and methods for forming the same are provided. The method for forming a semiconductor structure includes forming an N-well region in a substrate and forming a first protection layer over the N-well region. The method for forming a semiconductor structure further includes forming a P-well region in the substrate and forming a second protection layer over the P-well region. The method for forming a semiconductor structure further includes growing a first channel layer over the first protection layer and a second channel layer over the second protection layer and forming a first gate structure over the first channel layer and a second gate structure over the second channel layer.

公开(公告)号：US12080761B2

公开(公告)日：2024-09-03

申请号：US17582727

申请日：2022-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Huai-Tei Yang ,  Zheng-Yang Pan ,  Shih-Chieh Chang ,  Chun-Chieh Wang ,  Cheng-Han Lee

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/74 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1054 ,  H01L21/02057 ,  H01L21/02645 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/74 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7851 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02661

Abstract: The present disclosure describes an exemplary fin structure formed on a substrate. The disclosed fin structure comprises an n-type doped region formed on a top portion of the substrate, a silicon epitaxial layer on the n-type doped region, and an epitaxial stack on the silicon epitaxial layer, wherein the epitaxial stack comprises a silicon-based seed layer in physical contact with the silicon epitaxial layer. The fin structure can further comprise a liner surrounding the n-type doped region, and a dielectric surrounding the liner.

公开(公告)号：US11776851B2

公开(公告)日：2023-10-03

申请号：US17734521

申请日：2022-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yu Ma ,  Zheng-Yang Pan ,  Shahaji B. More ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L21/823418 ,  H01L21/0245 ,  H01L21/0262 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53257 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66348 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7848 ,  H01L21/02576 ,  H01L21/02579 ,  H01L29/165

Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.

公开(公告)号：US11152362B2

公开(公告)日：2021-10-19

申请号：US15348652

申请日：2016-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Chieh Wang ,  Zheng-Yang Pan ,  Yi-Min Huang ,  Shih-Chieh Chang ,  Tsung-Lin Lee

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure extending above a substrate, and the fin structure has a first portion and a second portion below the first portion, and the first portion and the second portion are made of different materials. The FinFET device structure includes an isolation structure formed on the substrate, and an interface between the first portion and the second portion of the fin structure is above a top surface of the isolation structure. The FinFET device structure includes a liner layer formed on sidewalls of the second portion of the fin structure.

公开(公告)号：US20210257263A1

公开(公告)日：2021-08-19

申请号：US17232381

申请日：2021-04-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Zheng-Yang Pan ,  Shih-Chieh Chang ,  Chun Chieh Wang

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L29/08 ,  H01L27/092 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49

Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.

公开(公告)号：US10535736B2

公开(公告)日：2020-01-14

申请号：US15719046

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Huai-Tei Yang ,  Zheng-Yang Pan ,  Shih-Chieh Chang ,  Chun-Chieh Wang ,  Cheng-Han Lee

IPC: H01L29/10 ,  H01L21/8238 ,  H01L21/74 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092 ,  H01L29/06

Abstract: The present disclosure describes an exemplary method to form p-type fully strained channel (PFSC) or an n-type fully strained channel (NFSC) that can mitigate epitaxial growth defects or structural deformations in the channel region due to processing. The exemplary method can include (i) two or more surface pre-clean treatment cycles with nitrogen trifluoride (NF3) and ammonia (NH3) plasma, followed by a thermal treatment; (ii) a prebake (anneal); and (iii) a silicon germanium epitaxial growth with a silicon seed layer, a silicon germanium seed layer, or a combination thereof.