公开(公告)号：US20230140968A1

公开(公告)日：2023-05-11

申请号：US18154087

申请日：2023-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hang Chiu ,  Chung-Chiang Wu ,  Jo-Chun Hung ,  Wei-Cheng Wang ,  Kuan-Ting Liu ,  Chi On Chui

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/28

CPC classification number: H01L29/4908 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/02603 ,  H01L29/66742 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66553 ,  H01L29/66545 ,  H01L21/28088

Abstract: Semiconductor devices having improved gate electrode structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; an n-type work function layer over the high-k dielectric layer; an anti-reaction layer over the n-type work function layer, the anti-reaction layer including a dielectric material; a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer; and a conductive cap layer over the p-type work function layer.

公开(公告)号：US20220359296A1

公开(公告)日：2022-11-10

申请号：US17870343

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Hsin-Han Tsai ,  Shih-Hang Chiu ,  Tsung-Ta Tang ,  Chung-Chiang Wu ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Da-Yuan Lee ,  Jian-Hao Chen ,  Chien-Hao Chen ,  Kuo-Feng Yu ,  Chia-Wei Chen ,  Chih-Yu Hsu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

公开(公告)号：US20220336619A1

公开(公告)日：2022-10-20

申请号：US17854749

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Hung-Chin Chung ,  Chung-Chiang Wu ,  Hsuan-Yu Tung ,  Kuan-Chang Chiu ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/8234

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.

公开(公告)号：US20220328316A1

公开(公告)日：2022-10-13

申请号：US17852960

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Shiung Tsai ,  Chung-Chiang Wu ,  Wei-Fan Liao ,  Han-Ti Hsiaw

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40

Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.

公开(公告)号：US11430698B2

公开(公告)日：2022-08-30

申请号：US16877708

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Han Tsai ,  Chung-Chiang Wu ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/49

Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.

公开(公告)号：US11380549B2

公开(公告)日：2022-07-05

申请号：US16939364

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Shiung Tsai ,  Chung-Chiang Wu ,  Wei-Fan Liao ,  Han-Ti Hsiaw

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/49 ,  H01L21/28

Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a metal layer is formed over a substrate using a fluorine-free deposition process, a nucleation layer is formed over the metal layer using a fluorine included deposition process, and a fill material is formed to fill an opening and form a gate stack.

公开(公告)号：US11302582B2

公开(公告)日：2022-04-12

申请号：US16686388

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yen Tsai ,  Chung-Chiang Wu ,  Tai-Wei Hwang ,  Hung-Chin Chung ,  Wei-Chin Lee ,  Da-Yuan Lee ,  Ching-Hwanq Su ,  Yin-Chuan Chuang ,  Kuan-Ting Liu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L29/51

Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

公开(公告)号：US11289480B2

公开(公告)日：2022-03-29

申请号：US17000632

申请日：2020-08-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Shih-Hang Chiu ,  Chih-Chang Hung ,  I-Wei Yang ,  Shu-Yuan Ku ,  Cheng-Lung Hung ,  Da-Yuan Lee ,  Ching-Hwanq Su

IPC: H01L27/088 ,  H01L29/06 ,  H01L27/11 ,  H01L21/8234 ,  H01L29/66

Abstract: A method includes forming a first semiconductor fin in a substrate, forming a metal gate structure over the first semiconductor fin, removing a portion of the metal gate structure to form a first recess in the metal gate structure that is laterally separated from the first semiconductor fin by a first distance, wherein the first distance is determined according to a first desired threshold voltage associated with the first semiconductor fin, and filling the recess with a dielectric material.

公开(公告)号：US20210273070A1

公开(公告)日：2021-09-02

申请号：US16889217

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Hung-Chin Chung ,  Chung-Chiang Wu ,  Hsuan-Yu Tung ,  Kuan-Chang Chiu ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/40

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.

公开(公告)号：US20210083118A1

公开(公告)日：2021-03-18

申请号：US16571879

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/40 ,  H01L21/8234

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.