中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

329 records (took 0.042 seconds)

    Semiconductor device with backside self-aligned power rail and methods of forming the same
    32.
    发明授权
    Semiconductor device with backside self-aligned power rail and methods of forming the same 有权

    公开(公告)号：US11444170B1

    公开(公告)日：2022-09-13

    申请号：US17199629

    申请日：2021-03-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chao Chou ,  Kuo-Cheng Chiang ,  Shi Ning Ju ,  Wen-Ting Lan ,  Chih-Hao Wang

    IPC: H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

    Gate patterning process for multi-gate devices
    34.
    发明授权
    Gate patterning process for multi-gate devices 有权

    公开(公告)号：US11387346B2

    公开(公告)日：2022-07-12

    申请号：US16858440

    申请日：2020-04-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

    IPC: H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/786

    Abstract: A method includes providing first and second channel layers in a p-type region and an n-type region respectively, forming a gate dielectric layer around the first and second channel layers, and forming a sacrificial layer around the gate dielectric layer. The sacrificial layer merges in space between the first channel layers and between the second channel layers. The method further includes etching the sacrificial layer such that only portions of the sacrificial layer in the space between the first channel layers and between the second channel layers remain, forming a mask covering the p-type region and exposing the n-type region, removing the sacrificial layer from the n-type region, removing the mask, and forming an n-type work function metal layer around the gate dielectric layer in the n-type region and over the gate dielectric layer and the sacrificial layer in the p-type region.

    Selective inner spacer implementations
    35.
    发明授权
    Selective inner spacer implementations 有权

    公开(公告)号：US11205711B2

    公开(公告)日：2021-12-21

    申请号：US16583388

    申请日：2019-09-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Pei-Hsun Wang ,  Kuo-Cheng Chiang ,  Lo-Heng Chang ,  Jung-Hung Chang ,  Chih-Hao Wang

    IPC: H01L29/66 ,  H01L21/306 ,  H01L29/08 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L27/11 ,  H01L29/10

    Abstract: A semiconductor device according to the present disclosure includes first gate-all-around (GAA) devices in a first device area and second GAA devices in a second device area. Each of the first GAA devices includes a first vertical stack of channel members, a first gate structure over and around the first vertical stack of channel members, and a plurality of inner spacer features. Each of the second GAA devices includes a second vertical stack of channel members and a second gate structure over and around the second vertical stack of channel members. Two adjacent channel members of the first vertical stack of channel members are separated by a portion of the first gate structure and at least one of the plurality of inner spacer features. Two adjacent channel members of the second vertical stack of channel members are separated only by a portion of the second gate structure.

    FINFET PITCH SCALING
    37.
    发明申请
    FINFET PITCH SCALING 有权

    公开(公告)号：US20210375860A1

    公开(公告)日：2021-12-02

    申请号：US16888457

    申请日：2020-05-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuan-Ting Pan ,  Yi-Ruei Jhan ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

    IPC: H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

    Abstract: According to one example, a semiconductor structure includes a first set of fin structures, a second set of fin structures, and a dielectric stack positioned between the first set of fin structures and the second set of fin structures. The dielectric stack has a top surface at substantially a same level as top surfaces of the first and second sets of fin structures. The dielectric stack includes a first dielectric material conforming to a bottom and sides of the dielectric stack, a second dielectric material along a top surface of the dielectric stack, and a third dielectric material in a middle of the dielectric stack. The semiconductor structure further includes a gate structure positioned over the first set of fin structures, the second set of fin structures and the dielectric stack.

    INTEGRATION OF MULTIPLE FIN STUCTURES ON A SINGLE SUBSTRATE
    39.
    发明申请
    INTEGRATION OF MULTIPLE FIN STUCTURES ON A SINGLE SUBSTRATE 有权

    公开(公告)号：US20210296312A1

    公开(公告)日：2021-09-23

    申请号：US16823581

    申请日：2020-03-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chao Chou ,  Chih-Hao Wang ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Wen-Ting Lan

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66

    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) including a first fin structure and a second fin structure vertically extending from a semiconductor substrate, respectively. The first fin structure laterally extends along a first direction and has a first width. The second fin structure laterally extends along the first direction and has a second width that is less than the first width. A first plurality of nanostructures directly overlies the first fin structure and is vertically spaced from the first fin structure by a non-zero distance. A gate electrode continuously laterally extends along a second direction that is substantially perpendicular to the first direction. The gate electrode directly overlies the first and second fin structures, and wraps around the nanostructures.

Patent Agency Ranking