公开(公告)号：US20200020709A1

公开(公告)日：2020-01-16

申请号：US16282045

申请日：2019-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han LIN ,  Wei Cheng WU

IPC: H01L27/11541 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L21/8239 ,  H01L21/306 ,  H01L21/285

Abstract: A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.

公开(公告)号：US20190088558A1

公开(公告)日：2019-03-21

申请号：US16195008

申请日：2018-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chen-Chin LIU

IPC: H01L21/8238 ,  H01L21/266 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/762 ,  H01L21/761

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

公开(公告)号：US20180315765A1

公开(公告)日：2018-11-01

申请号：US15904678

申请日：2018-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chin-Wen CHAN ,  Chih-Ren HSIEH

IPC: H01L27/11521 ,  H01L27/11519 ,  H01L21/762 ,  H01L29/06

Abstract: An integrated circuit includes a substrate, a first isolation feature, and a plurality of memory cells. The substrate has a cell region, a peripheral region, and a transition region between the cell region and the peripheral region. A top surface of the cell region is lower than a top surface of the peripheral region, and the substrate includes at least one protrusion portion in the transition region. The first isolation feature is in the transition region and covers the protrusion portion of the substrate. The memory cells are over the cell region of the substrate.

公开(公告)号：US20180090392A1

公开(公告)日：2018-03-29

申请号：US15782588

申请日：2017-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chen-Chin LIU

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/266 ,  H01L21/762 ,  H01L21/761

CPC classification number: H01L21/823892 ,  H01L21/266 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0928

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

公开(公告)号：US20180005897A1

公开(公告)日：2018-01-04

申请号：US15216569

申请日：2016-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chen-Chin LIU

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/762 ,  H01L29/423

CPC classification number: H01L21/823462 ,  H01L21/28158 ,  H01L21/76224 ,  H01L29/42364

Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of the substrate in plan view. A first dielectric layer is formed over the active region. A mask layer is formed on a gate region of the first dielectric layer. The gate region includes a region where a gate electrode is to be formed. The mask layer covers the gate region, but does not entirely cover the first dielectric layer. The first dielectric layer not covered by the mask layer is removed such that a source-drain region of the active region is exposed. After that, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. The gate electrode is formed over the gate dielectric layer.