公开(公告)号：US11133188B2

公开(公告)日：2021-09-28

申请号：US16716292

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ling Hsu ,  Hung-Ling Shih ,  Chieh-Fei Chiu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair ,  Shihkuang Yang

IPC: H01L21/28 ,  H01L29/423 ,  H01L27/11521 ,  H01L45/00 ,  H01L23/31 ,  H01L27/24 ,  H01L21/3105 ,  H01L27/11531 ,  H01L27/11548

Abstract: A method of manufacturing a non-volatile memory semiconductor device includes forming a plurality of memory cells on a non-volatile memory cell area of a semiconductor substrate, and forming a conductive layer over the plurality of memory cells. A first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise is formed over the plurality of memory cells. A planarization operation is performed on the first planarization layer and the conductive layer, thereby removing an upper region of the first planarization layer and an upper region of the conductive layer. Portions of a lower region of the conductive layer are completely removed between the memory cells.

公开(公告)号：US20210074360A1

公开(公告)日：2021-03-11

申请号：US16952411

申请日：2020-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Kuang Yang ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin

IPC: G11C16/08 ,  H01L27/108 ,  G11C11/16

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

公开(公告)号：US10861553B2

公开(公告)日：2020-12-08

申请号：US16400361

申请日：2019-05-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Kuang Yang ,  Ping-Cheng Li ,  Hung-Ling Shih ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Chia-Sheng Lin

IPC: G11C16/08 ,  H01L27/108 ,  G11C11/16

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

公开(公告)号：US20200219892A1

公开(公告)日：2020-07-09

申请号：US16822315

申请日：2020-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Ling Shih ,  Chieh-Fei Chiu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Shih Kuang Yang

IPC: H01L27/11521 ,  H01L29/788 ,  H01L21/308 ,  H01L21/768 ,  H01L21/027 ,  H01L21/762 ,  H01L21/28

Abstract: In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a pad stack over a semiconductor substrate, where the pad stack includes a lower pad layer and an upper pad layer. An isolation structure having a pair of isolation segments separated in a first direction by the pad stack is formed in the semiconductor substrate. The upper pad is removed to form an opening, where the isolation segments respectively have opposing sidewalls in the opening that slant at a first angle. A first etch is performed that partially removes the lower pad layer and isolation segments in the opening so the opposing sidewalls slant at a second angle greater than the first angle. A second etch is performed to round the opposing sidewalls and remove the lower pad layer from the opening. A floating gate is formed in the opening.

公开(公告)号：US09929167B2

公开(公告)日：2018-03-27

申请号：US15209370

申请日：2016-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsun-Kai Tsao ,  Hung-Ling Shih ,  Po-Wei Liu ,  Shun-Shing Yang ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair ,  S. K. Yang

IPC: H01L27/11529 ,  H01L21/28 ,  H01L21/3105

CPC classification number: H01L27/11529 ,  H01L21/28273 ,  H01L21/31056 ,  H01L27/11521 ,  H01L29/42328

Abstract: A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

公开(公告)号：US09287280B2

公开(公告)日：2016-03-15

申请号：US14326562

申请日：2014-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsun-Kai Tsao ,  Yong-Shiuan Tsair ,  Hung-Ling Shih ,  Po-Wei Liu ,  Wen-Tuo Huang

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/28273 ,  H01L21/32137 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate that includes a first source/drain region and a second source/drain region. The semiconductor structure further includes an erase gate located over the first source/drain region, and a word line and a floating gate located over the semiconductor substrate between the first and second source/drain regions. The floating gate is arranged between the word line and the erase gate. Further, the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate. A method of manufacturing the semiconductor structure using a high selectively etch recipe, such as an etch recipe comprised of primarily hydrogen bromide (HBr) and oxygen, is also provided.

Abstract translation: 提供了分离栅闪存单元的半导体结构。 半导体结构包括包括第一源极/漏极区域和第二源极/漏极区域的半导体衬底。 半导体结构还包括位于第一源极/漏极区域上方的擦除栅极以及位于第一和第二源极/漏极区域之间的位于半导体衬底之上的字线和浮置栅极。 浮栅位于字线与擦除栅之间。 此外，浮动栅极包括从浮动栅极的顶表面垂直向上延伸并且分别布置在浮动栅极的相对侧上的一对突起。 还提供了使用高选择性蚀刻配方制造半导体结构的方法，例如主要由溴化氢（HBr）和氧组成的蚀刻配方。

公开(公告)号：US20150021679A1

公开(公告)日：2015-01-22

申请号：US13945002

申请日：2013-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yong-Shiuan Tsair ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Tsun-Kai Tsao ,  Ming-Huei Shen

IPC: H01L29/788 ,  H01L29/66

CPC classification number: H01L27/11517 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

Abstract: Some embodiments of the present disclosure relates to an architecture to create split gate flash memory cell that has lower common source (CS) resistance and a reduced cell size by utilizing a buried conductive common source structure. A two-step etch process is carried out to create a recessed path between two split gate flash memory cells. A single ion implantation to form the common source also forms a conductive path beneath the STI region that connects two split gate flash memory cells and provide potential coupling during programming and erasing and thus electrically connect the common sources of memory cells along a direction that forms a CS line. The architecture contains no OD along the source line between the cells, thus eliminating the effects of CS rounding and CS resistance, resulting in a reduced space between cells in an array. Hence, this particular architecture reduces the resistance and the buried conductive path between several cells in an array suppresses the area over head.

Abstract translation: 本公开的一些实施例涉及通过利用埋入式导电公共源结构来创建具有较低共同源（CS）电阻和减小的单元尺寸的分离栅极闪存单元的架构。 执行两步蚀刻工艺以在两个分离栅极闪存单元之间形成凹陷路径。 用于形成公共源的单个离子注入还在STI区域下方形成连接两个分离栅极快速存储器单元的导电路径，并且在编程和擦除期间提供电位耦合，从而沿共同的方向电连接存储器单元的方向 CS线。 该架构沿单元格之间的源极线不包含OD，从而消除CS舍入和CS电阻的影响，导致阵列中单元之间的空间减小。 因此，这种特定的结构降低了电阻，并且阵列中的几个单元之间的掩埋导电路径抑制了头上的区域。