公开(公告)号：US10680002B2

公开(公告)日：2020-06-09

申请号：US15981056

申请日：2018-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Ling Shih ,  Chieh-Fei Chiu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Shih Kuang Yang

IPC: H01L21/311 ,  H01L27/11521 ,  H01L29/788 ,  H01L21/308 ,  H01L21/768 ,  H01L21/027 ,  H01L21/762 ,  H01L21/28

Abstract: In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a pad stack over a semiconductor substrate, where the pad stack includes a lower pad layer and an upper pad layer. An isolation structure having a pair of isolation segments separated in a first direction by the pad stack is formed in the semiconductor substrate. The upper pad is removed to form an opening, where the isolation segments respectively have opposing sidewalls in the opening that slant at a first angle. A first etch is performed that partially removes the lower pad layer and isolation segments in the opening so the opposing sidewalls slant at a second angle greater than the first angle. A second etch is performed to round the opposing sidewalls and remove the lower pad layer from the opening. A floating gate is formed in the opening.

公开(公告)号：US11637113B2

公开(公告)日：2023-04-25

申请号：US17226348

申请日：2021-04-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： ShihKuang Yang ,  Yong-Shiuan Tsair ,  Po-Wei Liu ,  Hung-Ling Shih ,  Yu-Ling Hsu ,  Chieh-Fei Chiu ,  Wen-Tuo Huang

IPC: H01L29/788 ,  H01L27/11521 ,  H01L29/423 ,  H01L21/28 ,  H01L29/78

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°

公开(公告)号：US11296147B2

公开(公告)日：2022-04-05

申请号：US16413716

申请日：2019-05-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chieh-Fei Chiu ,  Yong-Shiuan Tsair ,  Wen-Ting Chu ,  Yu-Wen Liao ,  Chin-Yu Mei ,  Po-Hao Tseng

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.

公开(公告)号：US11107982B2

公开(公告)日：2021-08-31

申请号：US16601800

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Fei Chiu ,  Wen-Ting Chu ,  Yong-Shiuan Tsair ,  Yu-Wen Liao ,  Chin-Yu Mei ,  Po-Hao Tseng

IPC: H01L45/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/48

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a lower inter-level dielectric (ILD) structure surrounding a plurality of lower interconnect layers over a substrate. An etch stop material is disposed over the lower ILD structure. A bottom electrode is arranged over an upper surface of the etch stop material, a data storage structure is disposed on an upper surface of the bottom electrode and is configured to store a data state, and a top electrode is disposed on an upper surface of the data storage structure. A first interconnect via contacts the upper surface the bottom electrode and a second interconnect via contacts the top electrode.

公开(公告)号：US12232333B2

公开(公告)日：2025-02-18

申请号：US18361483

申请日：2023-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chieh-Fei Chiu ,  Wen-Ting Chu ,  Yong-Shiuan Tsair ,  Yu-Wen Liao ,  Chih-Yang Chang ,  Chin-Chieh Yang

IPC: H10N70/20 ,  H10B51/30 ,  H10B51/40 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/00

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

公开(公告)号：US11751405B2

公开(公告)日：2023-09-05

申请号：US17032155

申请日：2020-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chieh-Fei Chiu ,  Wen-Ting Chu ,  Yong-Shiuan Tsair ,  Yu-Wen Liao ,  Chih-Yang Chang ,  Chin-Chieh Yang

IPC: H01L45/00 ,  H10B63/00 ,  H10B51/30 ,  H10B51/40 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/30 ,  H10B51/30 ,  H10B51/40 ,  H10B61/22 ,  H10N50/01 ,  H10N50/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/068 ,  H10N70/231 ,  H10N70/253 ,  H10N70/841

Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a dielectric layer over a conductive feature; etching an opening in the dielectric layer to expose the conductive feature, such that the dielectric layer has a tapered sidewall surrounding the opening; depositing a bottom electrode layer into the opening in the dielectric layer; depositing a resistance switch layer over the bottom electrode layer; patterning the resistance switch layer and the bottom electrode layer respectively into a resistance switch element and a bottom electrode, in which a sidewall of the bottom electrode is landing on the tapered sidewall of the dielectric layer.

公开(公告)号：US20190355731A1

公开(公告)日：2019-11-21

申请号：US15981056

申请日：2018-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Ling Shih ,  Chieh-Fei Chiu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Shih Kuang Yang

IPC: H01L27/11521 ,  H01L29/788 ,  H01L21/28 ,  H01L21/762 ,  H01L21/768 ,  H01L21/027 ,  H01L21/308

Abstract: In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a pad stack over a semiconductor substrate, where the pad stack includes a lower pad layer and an upper pad layer. An isolation structure having a pair of isolation segments separated in a first direction by the pad stack is formed in the semiconductor substrate. The upper pad is removed to form an opening, where the isolation segments respectively have opposing sidewalls in the opening that slant at a first angle. A first etch is performed that partially removes the lower pad layer and isolation segments in the opening so the opposing sidewalls slant at a second angle greater than the first angle. A second etch is performed to round the opposing sidewalls and remove the lower pad layer from the opening. A floating gate is formed in the opening.

公开(公告)号：US10269815B2

公开(公告)日：2019-04-23

申请号：US15498743

申请日：2017-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： ShihKuang Yang ,  Hung-Ling Shih ,  Chieh-Fei Chiu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair

IPC: H01L21/04 ,  H01L27/11521 ,  H01L29/423 ,  H01L21/306 ,  H01L21/3065

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°

公开(公告)号：US11189627B2

公开(公告)日：2021-11-30

申请号：US16822315

申请日：2020-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Ling Shih ,  Chieh-Fei Chiu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Ling Hsu ,  Yong-Shiuan Tsair ,  Shih Kuang Yang

IPC: H01L29/778 ,  H01L27/11521 ,  H01L29/788 ,  H01L21/308 ,  H01L21/768 ,  H01L21/027 ,  H01L21/762 ,  H01L21/28

Abstract: In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a pad stack over a semiconductor substrate, where the pad stack includes a lower pad layer and an upper pad layer. An isolation structure having a pair of isolation segments separated in a first direction by the pad stack is formed in the semiconductor substrate. The upper pad is removed to form an opening, where the isolation segments respectively have opposing sidewalls in the opening that slant at a first angle. A first etch is performed that partially removes the lower pad layer and isolation segments in the opening so the opposing sidewalls slant at a second angle greater than the first angle. A second etch is performed to round the opposing sidewalls and remove the lower pad layer from the opening. A floating gate is formed in the opening.

公开(公告)号：US11133188B2

公开(公告)日：2021-09-28

申请号：US16716292

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Ling Hsu ,  Hung-Ling Shih ,  Chieh-Fei Chiu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yong-Shiuan Tsair ,  Shihkuang Yang

IPC: H01L21/28 ,  H01L29/423 ,  H01L27/11521 ,  H01L45/00 ,  H01L23/31 ,  H01L27/24 ,  H01L21/3105 ,  H01L27/11531 ,  H01L27/11548

Abstract: A method of manufacturing a non-volatile memory semiconductor device includes forming a plurality of memory cells on a non-volatile memory cell area of a semiconductor substrate, and forming a conductive layer over the plurality of memory cells. A first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise is formed over the plurality of memory cells. A planarization operation is performed on the first planarization layer and the conductive layer, thereby removing an upper region of the first planarization layer and an upper region of the conductive layer. Portions of a lower region of the conductive layer are completely removed between the memory cells.