公开(公告)号：US11410877B2

公开(公告)日：2022-08-09

申请号：US17078677

申请日：2020-10-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu

IPC: H01L29/41 ,  H01L21/768 ,  H01L21/308 ,  H01L29/417 ,  H01L21/265 ,  H01L29/66 ,  H01L21/8234

Abstract: Source/drain contact spacers for improving integrated circuit device performance and methods of forming such are disclosed herein. An exemplary method includes etching an interlayer dielectric (ILD) layer to form a source/drain contact opening that exposes a contact etch stop layer (CESL) disposed over a source/drain feature, depositing a source/drain contact spacer layer that partially fills the source/drain contact opening and covers the ILD layer and the exposed CESL, and etching the source/drain contact spacer layer and the CESL to extend the source/drain contact opening to expose the source/drain feature. The etching forms source/drain contact spacers. The method further includes forming a source/drain contact to the exposed source/drain feature in the extended source/drain contact opening. The source/drain contact is formed over the source/drain contact spacers and fills the extended source/drain contact opening. A silicide feature can be formed over the exposed source/drain feature before forming the source/drain contact.

公开(公告)号：US11328982B2

公开(公告)日：2022-05-10

申请号：US16817111

申请日：2020-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Youbo Lin

IPC: H01L23/482 ,  H01L23/498 ,  H01L21/768 ,  H01L21/764 ,  H01L29/417 ,  H01L29/49

Abstract: Interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the interconnects are disclosed herein. An exemplary interconnect is disposed in an insulating layer. The interconnect has a metal contact, a contact isolation layer surrounding sidewalls of the metal contact, and an air gap disposed between the contact isolation layer and the insulating layer. An air gap seal for the air gap has a first portion disposed over a top surface of the contact isolation layer, but not disposed on a top surface of the insulating layer, and a second portion disposed between the contact isolation layer and the insulating layer, such that the second portion surrounds a top portion of sidewalls of the metal contact. The air gap seal may include amorphous silicon and/or silicon oxide. The contact isolation layer may include silicon nitride. The insulating layer may include silicon oxide.

公开(公告)号：US11094821B2

公开(公告)日：2021-08-17

申请号：US16573898

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Youbo Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L29/40

Abstract: The present disclosure provides a method that includes forming a gate stack on a semiconductor substrate; forming an etch stop layer on the gate stack and the semiconductor substrate; depositing a dielectric liner layer on the etch stop layer; performing an anisotropic etch to selectively remove portions of the dielectric liner layer such that the etch stop layer is exposed on top surfaces of the gate stack and the semiconductor substrate; depositing a silicon layer selectively on exposed surfaces of the etch stop layer; depositing an inter-layer dielectric (ILD) layer on the gate stack and the semiconductor substrate; and performing an anneal to oxidize the silicon layer, thereby generating a compressive stress to a channel region underlying the gate stack.

公开(公告)号：US20210083113A1

公开(公告)日：2021-03-18

申请号：US17099142

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Huiling Shang

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/225 ,  H01L21/02

Abstract: Examples of an integrated circuit with a strain-generating liner and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, and a gate disposed on the fin. The gate has a bottom portion disposed towards the fin and a top portion disposed on the bottom portion. A liner is disposed on a side surface of the bottom portion of the gate such that the top portion of the gate is free of the liner. In some such examples, the liner is configured to produce a channel strain.

公开(公告)号：US20200035549A1

公开(公告)日：2020-01-30

申请号：US16217676

申请日：2018-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu

IPC: H01L21/768 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/66 ,  H01L29/417

Abstract: Source/drain contact spacers for improving integrated circuit device performance and methods of forming such are disclosed herein. An exemplary method includes etching an interlevel dielectric (ILD) layer to form a source/drain contact opening that exposes a contact etch stop layer (CESL) disposed over a source/drain feature, depositing a source/drain contact spacer layer that partially fills the source/drain contact opening and covers the ILD layer and the exposed CESL, and etching the source/drain contact spacer layer and the CESL to extend the source/drain contact opening to expose the source/drain feature. The etching forms source/drain contact spacers. The method further includes forming a source/drain contact to the exposed source/drain feature in the extended source/drain contact opening. The source/drain contact is formed over the source/drain contact spacers and fills the extended source/drain contact opening. A silicide feature can be formed over the exposed source/drain feature before forming the source/drain contact.

公开(公告)号：US20240387281A1

公开(公告)日：2024-11-21

申请号：US18787051

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Lun Min ,  Xusheng Wu ,  Chang-Miao Liu

IPC: H01L21/8234 ,  H01L21/764 ,  H01L27/088

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

公开(公告)号：US12148669B2

公开(公告)日：2024-11-19

申请号：US18524527

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Ying-Keung Leung ,  Huiling Shang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.

公开(公告)号：US12113118B2

公开(公告)日：2024-10-08

申请号：US17815181

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bwo-Ning Chen ,  Xusheng Wu ,  Chang-Miao Liu ,  Shih-Hao Lin

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/06 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/76832 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method includes forming a silicon liner over a semiconductor device, which includes a dummy gate structure disposed over a substrate and S/D features disposed adjacent to the dummy gate structure, where the dummy gate structure traverses a channel region between the S/D features. The method further includes forming an ILD layer over the silicon liner, which includes elemental silicon, introducing a dopant species to the ILD layer, and subsequently removing the dummy gate structure to form a gate trench. Thereafter, the method proceeds to performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner, and forming a metal gate stack in the gate trench and over the oxidized silicon liner.

公开(公告)号：US12100625B2

公开(公告)日：2024-09-24

申请号：US18358708

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Lun Min ,  Xusheng Wu ,  Chang-Miao Liu

IPC: H01L27/088 ,  H01L21/764 ,  H01L21/8234

CPC classification number: H01L21/823481 ,  H01L21/764 ,  H01L21/823431 ,  H01L27/0886

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

公开(公告)号：US20240105517A1

公开(公告)日：2024-03-28

申请号：US18524527

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Ying-Keung Leung ,  Huiling Shang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823418 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/088 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/78696

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor stack over a substrate, wherein the first semiconductor stack includes first semiconductor layers separated from each other and stacked up along a direction substantially perpendicular to a top surface of the substrate; second semiconductor stack over the substrate, wherein the second semiconductor stack includes second semiconductor layers separated from each other and stacked up along the direction substantially perpendicular to the top surface of the substrate; inner spacers between edge portions of the first semiconductor layers and between edge portions of the second semiconductor layers; and a bulk source/drain (S/D) feature between the first semiconductor stack and the second semiconductor stack, wherein the bulk S/D feature is separated from the substrate by a first air gap, and the bulk S/D feature is separated from the inner spacers by second air gaps.