公开(公告)号：US11594680B2

公开(公告)日：2023-02-28

申请号：US17463790

申请日：2021-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Miao Liu ,  Bwo-Ning Chen ,  Kei-Wei Chen

IPC: H01L45/00

Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.

公开(公告)号：US20220384618A1

公开(公告)日：2022-12-01

申请号：US17877221

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Jui-Lin Chen ,  Hsin-Wen Su ,  Kian-Long Lim ,  Bwo-Ning Chen ,  Chih-Hsuan Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

公开(公告)号：US11133386B2

公开(公告)日：2021-09-28

申请号：US16735379

申请日：2020-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bwo-Ning Chen ,  Xusheng Wu ,  Chang-Miao Liu

IPC: H01L29/10 ,  H01L27/092 ,  H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/265

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The structure includes a semiconductor substrate; a fin extending above the semiconductor substrate, wherein the fin includes a first layer over the semiconductor substrate and a second layer over the first layer, wherein the first layer includes silicon germanium having a first concentration of germanium, and wherein the second layer includes silicon germanium having a second concentration of germanium less than the first concentration of germanium; and a gate stack disposed over the fin.

公开(公告)号：US11728405B2

公开(公告)日：2023-08-15

申请号：US16820175

申请日：2020-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bwo-Ning Chen ,  Xusheng Wu ,  Chang-Miao Liu ,  Shih-Hao Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L21/768 ,  H01L29/165

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/76832 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7848

Abstract: A semiconductor structure includes source/drain (S/D) features disposed over a semiconductor substrate, a metal gate stack disposed between the S/D features, where the metal gate stack traverses a channel region between the S/D features, gate spacers disposed on sidewalls of the metal gate stack, and an etch-stop layer (ESL) disposed over the gate spacers and the S/D features. The semiconductor structure further includes an oxide liner disposed on the ESL, where the oxide liner includes silicon oxide and silicon dioxide, and an interlayer dielectric (ILD) layer disposed on the oxide liner, where composition of the ILD layer is different from composition of the oxide liner.

公开(公告)号：US20230200264A1

公开(公告)日：2023-06-22

申请号：US18172762

申请日：2023-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Miao Liu ,  Bwo-Ning Chen ,  Kei-Wei Chen

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/063 ,  H10N70/231 ,  H10N70/253

Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.

公开(公告)号：US20210399221A1

公开(公告)日：2021-12-23

申请号：US17463790

申请日：2021-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Miao Liu ,  Bwo-Ning Chen ,  Kei-Wei Chen

IPC: H01L45/00

Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.

公开(公告)号：US11081401B2

公开(公告)日：2021-08-03

申请号：US16699496

申请日：2019-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bwo-Ning Chen ,  Xu-Sheng Wu ,  Chang-Miao Liu

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L21/02

Abstract: A method for manufacturing a semiconductor device, includes: forming a shallow trench isolation structure surrounding a first semiconductor fin and a second semiconductor fin; forming a dummy gate structure across the first and second semiconductor fins; forming a first flowable dielectric layer over the first and second semiconductor fins; curing the first flowable dielectric layer at a first temperature; removing a first portion of the cured first flowable dielectric layer from above the second semiconductor fin; after removing the first portion of the cured first flowable dielectric layer, forming a second flowable dielectric layer over the second semiconductor fin; curing the second flowable dielectric layer at a second temperature different from the first temperature; and replacing the dummy gate structure with a metal gate structure.

公开(公告)号：US12113118B2

公开(公告)日：2024-10-08

申请号：US17815181

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bwo-Ning Chen ,  Xusheng Wu ,  Chang-Miao Liu ,  Shih-Hao Lin

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/06 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/76832 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method includes forming a silicon liner over a semiconductor device, which includes a dummy gate structure disposed over a substrate and S/D features disposed adjacent to the dummy gate structure, where the dummy gate structure traverses a channel region between the S/D features. The method further includes forming an ILD layer over the silicon liner, which includes elemental silicon, introducing a dopant species to the ILD layer, and subsequently removing the dummy gate structure to form a gate trench. Thereafter, the method proceeds to performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner, and forming a metal gate stack in the gate trench and over the oxidized silicon liner.

公开(公告)号：US11482610B2

公开(公告)日：2022-10-25

申请号：US16931717

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Jui-Lin Chen ,  Hsin-Wen Su ,  Kian-Long Lim ,  Bwo-Ning Chen ,  Chih-Hsuan Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

公开(公告)号：US20210098604A1

公开(公告)日：2021-04-01

申请号：US16931717

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Jui-Lin Chen ,  Hsin-Wen Su ,  Kian-Long Lim ,  Bwo-Ning Chen ,  Chih-Hsuan Chen

IPC: H01L29/66 ,  H01L21/3115 ,  H01L29/78

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.