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    SEMICONDUCTOR DEVICE
    31.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：US20100276732A1

    公开(公告)日：2010-11-04

    申请号：US12810096

    申请日：2008-12-25

    申请人： Yuji Ando ,  Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

    发明人： Yuji Ando ,  Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66462 ,  H01L27/0605 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/7781

    摘要： A semiconductor device includes a lower barrier layer 12 composed of a layer of AlxGa1-xN (0≦x≦1) in a state of strain relaxation, and a channel layer 13, which is composed of a layer of InyGa1-yN (0≦y≦1) disposed on the lower barrier layer 12, has band gap that is smaller than band gap of the lower barrier layer 12, and exhibits compressive strain. A gate electrode 1G is formed over the channel layer 13 via an insulating film 15 and a source electrode 1S and a drain electrode 1D serving as ohmic electrodes are formed over the channel layer 13. The insulating film 15 is constituted of polycrystalline or amorphous member.

    摘要翻译： 半导体器件包括在应变松弛的状态下由Al x Ga 1-x N（0＆amp; nlE; x＆nlE; 1）层构成的下阻挡层12，以及由In y Ga 1-y N（0＆lt; nlE; 1）层组成的沟道层13。 y）; 1）设置在下阻挡层12上，具有小于下阻挡层12的带隙的带隙，并且表现出压缩应变。 在沟道层13上经由绝缘膜15形成栅极电极1G，在沟道层13上形成有用作欧姆电极的源电极1S和漏电极1D。绝缘膜15由多晶或非晶构成。

    SEMICONDUCTOR DEVICE
    32.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20100230684A1

    公开(公告)日：2010-09-16

    申请号：US12299542

    申请日：2007-05-07

    申请人： Yasuhiro Okamoto ,  Yuji Ando ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

    发明人： Yasuhiro Okamoto ,  Yuji Ando ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

    IPC分类号： H01L29/80 ,  H01L29/205

    CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/42316

    摘要： A semiconductor device includes a channel layer, an electron-supplying layer provided on the channel layer, a cap layer provided on the electron-supplying layer and creating lattice match with the channel layer, and ohmic electrodes provided on the cap layer. The cap layer has a composition of (InyAl1-y)zGa1-zN (0≦y≦1, 0≦z≦1). The z for such cap layer monotonically decreases as being farther away from the electron-supplying layer.

    摘要翻译： 半导体器件包括沟道层，设置在沟道层上的电子供给层，设置在电子供给层上并与沟道层形成晶格匹配的盖层以及设置在盖层上的欧姆电极。 盖层具有（InyAl1-y）zGa1-zN（0＆nlE; y＆nlE; 1,0＆amp; nlE; z＆nlE; 1）的组成。 这种盖层的z随着远离电子供应层而单调减小。

    III-NITRIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR
    33.
    发明申请
    III-NITRIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR 有权
    III-NITRIDE半导体场效应晶体管

    公开(公告)号：US20100038680A1

    公开(公告)日：2010-02-18

    申请号：US12528578

    申请日：2008-02-26

    申请人： Tatsuo Nakayama ,  Yuji Ando ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Takashi Inoue

    发明人： Tatsuo Nakayama ,  Yuji Ando ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Takashi Inoue

    IPC分类号： H01L29/778

    CPC分类号： H01L29/42316 ,  H01L29/2003 ,  H01L29/7781

    摘要： Provided is a semiconductor device that can reduce the contact resistance, has a small current collapse, and can improve the pinch-off characteristic upon a high-frequency operation. A field effect transistor using a wurtzite (having (0001) as the main plane) type III-nitride semiconductor includes: a substrate (101); an undercoat layer (103) of a first III-nitride semiconductor; and a carrier travel layer (104) of a second III-nitride semiconductor. The undercoat layer (103) (101) and the carrier travel layer (104) is formed on the substrate in this order. The field effect transistor includes source/drain electrodes (105, 106) in ohmic contact, and a gate electrode (107) in Schottky contact directly or via another layer on the carrier travel layer (104). The undercoat layer (103) has an average lattice constant greater than that of the carrier travel layer (104) and a band gap greater than that of the carrier travel layer (104).

    摘要翻译： 提供了能够降低接触电阻，具有小的电流崩溃的半导体器件，并且可以在高频操作时提高夹断特性。 使用纤锌矿（具有（0001）作为主面）的III型氮化物半导体的场效应晶体管包括：衬底（101）; 第一III族氮化物半导体的底涂层（103） 和第二III族氮化物半导体的载流子行进层（104）。 底涂层（103）（101）和载体移动层（104）依次形成在基板上。 场效应晶体管包括欧姆接触的源极/漏极（105,106）和直接或通过载流子行进层（104）上的另一层的肖特基接触的栅电极（107）。 底涂层（103）的平均晶格常数大于载体移动层（104）的平均晶格常数，并且带隙大于载流子行进层（104）的平均晶格常数。

    Semiconductor device, field-effect transistor, and electronic device
    37.
    发明授权
    Semiconductor device, field-effect transistor, and electronic device 有权
    半导体器件，场效应晶体管和电子器件

    公开(公告)号：US08659055B2

    公开(公告)日：2014-02-25

    申请号：US13497557

    申请日：2010-06-16

    申请人： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

    发明人： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

    IPC分类号： H01L29/66 ,  H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66734

    摘要： Provided is a semiconductor device capable of suppressing an occurrence of a punch-through phenomenon.A semiconductor device includes a substrate 1, a first n-type semiconductor layer 2, a p-type semiconductor layer 3, a second n-type semiconductor layer 4, a drain electrode 13, a source electrode 11, a gate electrode 12, and a gate insulation film 21, wherein the first n-type semiconductor layer 2, the p-type semiconductor layer 3, and the second n-type semiconductor layer 4 are laminated on the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 2. The source electrode 11 is in ohmic-contact with the second n-type semiconductor layer 4. An opening portion to be filled or a notched portion that extends from an upper surface of the second n-type semiconductor layer 4 to an upper part of the first n-type semiconductor layer 2 is formed at a part of the p-type semiconductor layer 3 and a part of the second n-type semiconductor layer 4. The gate electrode 12 is in contact with an upper surface of the first n-type semiconductor layer 2, side surfaces of the p-type semiconductor layer 3, and side surfaces of the second n-type semiconductor layer 4 at inner surfaces of the opening portion to be filled or a surface of the notched portion via the gate insulation film 21. The p-type semiconductor layer 3 has a positive polarization charge at a first n-type semiconductor layer 2 side in a state where a voltage is applied to none of the electrodes.

    摘要翻译： 提供能够抑制穿通现象发生的半导体装置。 半导体器件包括衬底1，第一n型半导体层2，p型半导体层3，第二n型半导体层4，漏极13，源电极11，栅电极12和 栅极绝缘膜21，其中第一n型半导体层2，p型半导体层3和第二n型半导体层4依次层压在基板1上。 漏电极13与第一n型半导体层2欧姆接触。源电极11与第二n型半导体层4欧姆接触。要填充的开口部分或延伸的缺口部分 从第二n型半导体层4的上表面到第一n型半导体层2的上部形成在p型半导体层3的一部分上，第二n型半导体层的一部分 栅电极12与第一n型半导体层2的上表面，p型半导体层3的侧表面和第二n型半导体层4的内表面的侧表面接触 待填充的开口部分或经由栅极绝缘膜21的切口部分的表面。在施加电压的状态下，p型半导体层3在第一n型半导体层2侧具有正极化电荷 没有电极。

    Semiconductor apparatus having reverse blocking characteristics and method of manufacturing the same
    38.
    发明授权
    Semiconductor apparatus having reverse blocking characteristics and method of manufacturing the same 失效
    具有反向阻挡特性的半导体装置及其制造方法

    公开(公告)号：US08552471B2

    公开(公告)日：2013-10-08

    申请号：US13139789

    申请日：2009-12-11

    申请人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Kazuomi Endo

    发明人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Kazuomi Endo

    IPC分类号： H01L29/66

    CPC分类号： H01L29/402 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7787

    摘要： There is provided a semiconductor apparatus capable of achieving both a reverse blocking characteristic and a low on-resistance. The semiconductor apparatus includes a first semiconductor layer including a channel layer, a source electrode formed on the first semiconductor layer, a drain electrode formed at a distance from the source electrode on the first semiconductor layer, and a gate electrode formed between the source electrode and the drain electrode on the first semiconductor layer. The drain electrode includes a first drain region where reverse current between the first semiconductor layer and the first drain region is blocked, and a second drain region formed at a greater distance from the gate electrode than the first drain region, where a resistance between the first semiconductor layer and the second drain region is lower than a resistance between the first semiconductor layer and the first drain region.

    摘要翻译： 提供了能够实现反向阻挡特性和低导通电阻的半导体装置。 半导体装置包括：第一半导体层，包括沟道层，形成在第一半导体层上的源电极，在第一半导体层上与源极间隔一定距离处形成的漏电极，以及形成在源电极和 第一半导体层上的漏电极。 漏电极包括第一漏极区，其中第一半导体层和第一漏极区之间的反向电流被阻挡，以及形成在比栅极电极比第一漏极区更远的距离处的第二漏区， 半导体层和第二漏极区域比第一半导体层和第一漏极区域之间的电阻低。

    Group nitride bipolar transistor
    39.
    发明授权
    Group nitride bipolar transistor 有权
    组氮化物双极晶体管

    公开(公告)号：US08395237B2

    公开(公告)日：2013-03-12

    申请号：US13124872

    申请日：2009-10-16

    申请人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Kazuki Ota

    发明人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Kazuki Ota

    IPC分类号： H01L29/66 ,  H01L29/737

    CPC分类号： H01L29/7371 ,  H01L29/045 ,  H01L29/2003

    摘要： A bipolar transistor includes: a substrate; a collector and a base layer with a p-conductive-type, an emitter layer with an n-conductive-type. The collector layer is formed above the substrate and includes a first nitride semiconductor. The base layer with the p-conductive-type is formed on the collector layer and includes a second nit ride semiconductor. The emitter layer with the n-conductive-type is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed so that crystal growing directions with respect to a surface of the substrate are in parallel to a [0001] direction of the substrate. The first nitride semiconductor includes: InycAlxcGa1-xc-ycN (0≦xc≦1, 0≦yc≦1, 0

    摘要翻译： 双极晶体管包括：基板; 具有p导电型的集电极和基极层，具有n导电型的发射极层。 集电极层形成在衬底上方并且包括第一氮化物半导体。 具有p型导电型的基底层形成在集电极层上，并且包括第二耐磨半导体。 具有n导电型的发射极层形成在基极层上并且包括第三氮化物半导体。 形成集电体层，基极层和发射极层，使得相对于基板的表面的晶体生长方向与基板的[0001]方向平行。 第一氮化物半导体包括：InycAlxcGa1-xc-ycN（0＆nlE; xc＆nlE; 1,0＆amp; nlE; yc＆nlE; 1,0

    SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THE SAME
    40.
    发明申请
    SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THE SAME 失效
    半导体装置及其制造方法

    公开(公告)号：US20110260217A1

    公开(公告)日：2011-10-27

    申请号：US13139789

    申请日：2009-12-11

    申请人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Kazuomi Endo

    发明人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Kazuomi Endo

    IPC分类号： H01L29/778 ,  H01L21/335

    CPC分类号： H01L29/402 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7787

    摘要： There is provided a semiconductor apparatus capable of achieving both a reverse blocking characteristic and a low on-resistance. The semiconductor apparatus includes a first semiconductor layer including a channel layer, a source electrode formed on the first semiconductor layer, a drain electrode formed at a distance from the source electrode on the first semiconductor layer, and a gate electrode formed between the source electrode and the drain electrode on the first semiconductor layer. The drain electrode includes a first drain region where reverse current between the first semiconductor layer and the first drain region is blocked, and a second drain region formed at a greater distance from the gate electrode than the first drain region, where a resistance between the first semiconductor layer and the second drain region is lower than a resistance between the first semiconductor layer and the first drain region.

    摘要翻译： 提供了能够实现反向阻挡特性和低导通电阻的半导体装置。 半导体装置包括：第一半导体层，包括沟道层，形成在第一半导体层上的源电极，在第一半导体层上与源极间隔一定距离处形成的漏电极，以及形成在源电极和 第一半导体层上的漏电极。 漏电极包括第一漏极区，其中第一半导体层和第一漏极区之间的反向电流被阻挡，以及形成在比栅极电极比第一漏极区更远的距离处的第二漏区， 半导体层和第二漏极区域比第一半导体层和第一漏极区域之间的电阻低。