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    FIELD EFFECT TRANSISTOR, AND MULTILAYERED EPITAXIAL FILM FOR USE IN PREPARATION OF FIELD EFFECT TRANSISTOR
    4.
    发明申请
    FIELD EFFECT TRANSISTOR, AND MULTILAYERED EPITAXIAL FILM FOR USE IN PREPARATION OF FIELD EFFECT TRANSISTOR 有权
    场效应晶体管和用于制备场效应晶体管的多层外延膜

    公开(公告)号：US20090045438A1

    公开(公告)日：2009-02-19

    申请号：US12159599

    申请日：2006-10-25

    申请人： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

    发明人： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

    IPC分类号： H01L29/205 ,  H01L29/80

    CPC分类号： H01L29/7783 ,  H01L29/0607 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7787

    摘要： In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≧5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.

    摘要翻译： 在III族氮化物型场效应晶体管中，本发明通过缓冲层中的残留载流子的传导来减少漏电流成分，并且可以实现击穿电压的提高，并提高载流子限制效应（载流子限制） 提高夹断特性的通道（抑制短路效应）。 例如，当将本发明应用于GaN型场效应晶体管时，除了沟道层的GaN之外，使用其中铝组成逐渐或逐步朝向顶部的组分调制（组成梯度）AlGaN层用作 缓冲层（杂质缓冲液）。 对于要制备的FET的栅极长度Lg，选择电子供给层和沟道层的层厚度的和a以满足Lg / a> = 5，并且在这种情况下， 在不超过5倍（约500）的范围内选择通道层，只要在室温下积聚在通道层中的二维电子气的德布罗意波长即可。

    FIELD EFFECT TRANSISTOR
    6.
    发明申请
    FIELD EFFECT TRANSISTOR 审中-公开
    场效应晶体管

    公开(公告)号：US20090267114A1

    公开(公告)日：2009-10-29

    申请号：US12295104

    申请日：2007-03-23

    申请人： Tatsuo Nakayama ,  Yuji Ando ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Murase ,  Naotaka Kuroda

    发明人： Tatsuo Nakayama ,  Yuji Ando ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Murase ,  Naotaka Kuroda

    IPC分类号： H01L29/772 ,  H01L29/205

    CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/8128

    摘要： A field effect transistor 100 includes a group III-V nitride semiconductor layer structure containing a hetero junction, a source electrode 105 and a drain electrode 106 formed on the group III-V nitride semiconductor layer structure to be spaced apart from each other; a gate electrode 110 arranged between the source electrode 105 and the drain electrode 106, and an insulating layer 107 provided over, and in contact with, the group III-V nitride semiconductor layer structure in a region between the gate electrode 110 and the drain electrode 106 or in a region between the source electrode 105 and the gate electrode 110. A portion of the gate electrode 110 is buried in the group III-V nitride semiconductor layer structure, and a side edge of the gate electrode in an interface of the group III-V nitride semiconductor layer and the insulating layer 107 is spaced apart from the gate electrode 110.

    摘要翻译： 场效应晶体管100包括在III-V族氮化物半导体层结构上彼此间隔开的含有异质结的III-V族氮化物半导体层结构，源电极105和漏电极106。 布置在源电极105和漏电极106之间的栅电极110以及在栅电极110和漏电极之间的区域中设置在III-V族氮化物半导体层结构上并与III-V族氮化物半导体层结构接触的绝缘层107 106或源极电极105和栅电极110之间的区域中。栅电极110的一部分被掩埋在III-V族氮化物半导体层结构中，并且栅极电极在该组的界面中的侧边缘 III-V族氮化物半导体层和绝缘层107与栅电极110间隔开。

    FIELD EFFECT TRANSISTOR
    7.
    发明申请
    FIELD EFFECT TRANSISTOR 有权
    场效应晶体管

    公开(公告)号：US20100224910A1

    公开(公告)日：2010-09-09

    申请号：US12295004

    申请日：2007-03-29

    申请人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Yasuhiro Murase ,  Kazuki Ota ,  Akio Wakejima ,  Naotaka Kuroda

    发明人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Yasuhiro Murase ,  Kazuki Ota ,  Akio Wakejima ,  Naotaka Kuroda

    IPC分类号： H01L29/80

    CPC分类号： H01L29/7787 ,  H01L29/2003

    摘要： Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0≦y≦1); a carrier supply layer 13 composed of AlxGa1-xN (0≦x≦1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x

    摘要翻译： 公开了一种HJFET 110，其包括：由In y Ga 1-y N（0＆lt; n 1; y＆n 1; 1）构成的沟道层12; 载体供给层13由Al x Ga 1-x N（0＆lt; n 1; x＆n 1; 1）组成，载流子供给层13设置在沟道层12上并且包括至少一个p型层; 以及源极电极15S，漏极电极15D和栅极电极17，其通过p型层面对沟道层12，并且设置在载流子供给层13上。满足以下关系式：5.6×10 11× NA×＆eegr×T [cm-2] <5.6×1013x，其中x表示载流子供应层的Al组成比，t表示p型层的厚度，NA表示杂质浓度，＆eegr; 表示活化比。

    Field Effect Transistor
    9.
    发明申请
    Field Effect Transistor 审中-公开
    场效应晶体管

    公开(公告)号：US20090173968A1

    公开(公告)日：2009-07-09

    申请号：US12097700

    申请日：2006-12-12

    申请人： Kouji Matsunaga ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Akio Wakejima ,  Yuji Ando ,  Hironobu Miyamoto ,  Takashi Inoue ,  Yasuhiro Murase

    发明人： Kouji Matsunaga ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Akio Wakejima ,  Yuji Ando ,  Hironobu Miyamoto ,  Takashi Inoue ,  Yasuhiro Murase

    IPC分类号： H01L29/205

    CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/66462

    摘要： A semiconductor device 100 contains an undoped GaN channel layer 105, an AlGaN electron donor layer 106 provided on the undoped GaN channel layer 105 as being brought into contact therewith, an undoped GaN layer 107 provided on the AlGaN electron donor layer 106, a source electrode 101 and a drain electrode 103 provided on the undoped GaN layer 107 as being spaced from each other, a recess 111 provided in the region between the source electrode 101 and the drain electrode 103, as being extended through the undoped GaN layer 107, a gate electrode 102 buried in the recess 111 as being brought into contact with the AlGaN electron donor layer 106 on the bottom surface thereof, and an SiN film 108 provided on the undoped GaN layer 107, in the region between the gate electrode 102 and the drain electrode 103.

    摘要翻译： 半导体器件100包含未掺杂的GaN沟道层105，设置在与其接触的未掺杂的GaN沟道层105上的AlGaN电子供体层106，设置在AlGaN电子供体层106上的未掺杂的GaN层107，源电极 101和设置在未掺杂的GaN层107上彼此间隔开的漏电极103，设置在源电极101和漏电极103之间的区域中的凹槽111延伸穿过未掺杂的GaN层107，栅极 埋入凹槽111中的电极102与其底表面上的AlGaN电子供体层106接触，以及设置在未掺杂的GaN层107上的SiN膜108，在栅电极102和漏极之间的区域 103。