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117 条记录 (耗时 0.037 秒)

    Memory device including memory controller
    31.
    发明授权
    Memory device including memory controller 有权
    内存设备包括内存控制器

    公开(公告)号：US08230301B2

    公开(公告)日：2012-07-24

    申请号：US13207733

    申请日：2011-08-11

    申请人： Hiroshi Sukegawa

    发明人： Hiroshi Sukegawa

    IPC分类号： H03M13/00

    CPC分类号： G06F13/385

    摘要： A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and sends an address in accordance with a result of the check, and a data correction circuit which corrects a value of data at the address that is sent, and sends the corrected value to the semiconductor memory.

    摘要翻译： 存储装置包括：包括多个存储单元的半导体存储器，以及包括临时存储数据的缓冲器的控制器，检查存储在缓冲器中并要存储在其中的数据的预定数据模式的数据模式检查电路 多个相邻的存储单元，并根据检查结果发送地址;以及数据校正电路，其对发送的地址上的数据值进行校正，并将校正后的值发送到半导体存储器 。

    Memory device including memory controller
    32.
    发明授权
    Memory device including memory controller 有权
    内存设备包括内存控制器

    公开(公告)号：US08028206B2

    公开(公告)日：2011-09-27

    申请号：US11862669

    申请日：2007-09-27

    申请人： Hiroshi Sukegawa

    发明人： Hiroshi Sukegawa

    IPC分类号： G11C16/10

    CPC分类号： G06F13/385

    摘要： A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and sends an address in accordance with a result of the check, and a data correction circuit which corrects a value of data at the address that is sent, and sends the corrected value to the semiconductor memory.

    摘要翻译： 存储装置包括：包括多个存储单元的半导体存储器，以及包括临时存储数据的缓冲器的控制器，检查存储在缓冲器中并要存储在其中的数据的预定数据模式的数据模式检查电路 多个相邻的存储单元，并根据检查结果发送地址;以及数据校正电路，其对发送的地址上的数据值进行校正，并将校正后的值发送到半导体存储器 。

    STILL IMAGE MEMORY DEVICE AND LIGHTING APPARATUS
    33.
    发明申请
    STILL IMAGE MEMORY DEVICE AND LIGHTING APPARATUS 审中-公开
    静态图像存储设备和照明设备

    公开(公告)号：US20100245623A1

    公开(公告)日：2010-09-30

    申请号：US12722132

    申请日：2010-03-11

    申请人： Sayako KASAHARA ,  Hiroshi Sukegawa

    发明人： Sayako KASAHARA ,  Hiroshi Sukegawa

    IPC分类号： H04N5/76

    CPC分类号： H04N5/772 ,  G08B13/19676 ,  H04N5/2256 ,  H04N5/907 ,  H04N7/17318 ,  H04N21/25816 ,  H04N21/4184 ,  H04N21/4223 ,  H04N21/42684 ,  H04N21/4334 ,  H04N21/4335 ,  H04N21/8153

    摘要： A still image memory device includes an imaging unit, a nonvolatile memory unit that includes a first memory area and a second memory area, and a control unit that controls the nonvolatile memory unit. The control unit includes a first processing unit that stores, in the first memory area, the image data output from the imaging unit; a second processing unit that, based on memory status of the first memory area, reads and compresses image data selected from a plurality of image data stored in the first memory area, stores compressed image data in the second memory area, and destroys the image data selected from the plurality of image data stored in the first memory area; and a third processing unit that, based on memory status of the second memory area, destroys compressed image data selected from a plurality of compressed image data stored in the second memory area.

    摘要翻译： 静止图像存储装置包括成像单元，包括第一存储区域和第二存储区域的非易失性存储单元，以及控制非易失性存储单元的控制单元。 控制单元包括：第一处理单元，其在第一存储区域中存储从成像单元输出的图像数据; 第二处理单元，其基于所述第一存储区域的存储器状态读取并压缩从存储在所述第一存储区域中的多个图像数据中选择的图像数据，将压缩图像数据存储在所述第二存储区域中，并且破坏所述图像数据 从存储在第一存储区域中的多个图像数据中选择; 以及第三处理单元，其基于所述第二存储区域的存储器状态，销毁从存储在所述第二存储区域中的多个压缩图像数据中选择的压缩图像数据。

    SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES
    35.
    发明申请
    SEMICONDUCTOR MEMORY SYSTEM INCLUDING A PLURALITY OF SEMICONDUCTOR MEMORY DEVICES 有权
    半导体存储器系统，包括多个半导体存储器件

    公开(公告)号：US20100097864A1

    公开(公告)日：2010-04-22

    申请号：US12645104

    申请日：2009-12-22

    申请人： Noboru SHIBATA ,  Hiroshi Sukegawa

    发明人： Noboru SHIBATA ,  Hiroshi Sukegawa

    IPC分类号： G11C16/04

    CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3459

    摘要： A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.

    摘要翻译： 通信线路连接到第一和第二芯片，并保持在第一信号电平。 监视电路将通信线路的信号电平从第一信号改变到第二信号电平，而第一和第二芯片中的一个使用大于参考电流的电流。 当通信线路的信号电平为第二信号电平时，第一和第二芯片中的另一个被控制为等待状态，该等待状态不转移到使用大于参考电流的电流的操作状态。

    Memory system combining flash EEPROM and FeRAM
    36.
    发明授权
    Memory system combining flash EEPROM and FeRAM 有权
    存储系统组合闪存EEPROM和FeRAM

    公开(公告)号：US07397686B2

    公开(公告)日：2008-07-08

    申请号：US11443388

    申请日：2006-05-31

    申请人： Daisaburo Takashima ,  Shuso Fujii ,  Takaya Suda ,  Hiroshi Sukegawa

    发明人： Daisaburo Takashima ,  Shuso Fujii ,  Takaya Suda ,  Hiroshi Sukegawa

    IPC分类号： G11C11/22 ,  G11C16/04 ,  G06F12/00

    CPC分类号： G11C14/00 ,  G06F12/0246 ,  G06F2212/7207 ,  G11C7/1075 ,  G11C11/22 ,  G11C16/0483

    摘要： A memory system includes a ferroelectric memory formed by arranging a plurality of memory cells having a ferroelectric capacitor and cell transistor, a flash EEPROM formed by arranging a plurality of memory cells having a floating gate and capable of electrically erasing and writing data, a control circuit configured to control the ferroelectric memory and flash EEPROM, and an interface circuit configured to communicate with the outside. The flash EEPROM stores data. The ferroelectric memory stores at least one of root information for storing the data, directory information, the file name of the data, the file size of the data, file allocation table information storing the storage location of the data, and the write completion time of the data.

    摘要翻译： 存储器系统包括通过布置具有铁电电容器和单元晶体管的多个存储单元形成的铁电存储器，通过布置具有浮动栅极并能够电擦除和写入数据的多个存储单元形成的快闪EEPROM，控制电路 被配置为控制铁电存储器和闪存EEPROM，以及被配置为与外部通信的接口电路。 闪存EEPROM存储数据。 铁电存储器存储用于存储数据的根信息，目录信息，数据的文件名，数据的文件大小，存储数据的存储位置的文件分配表信息和写入完成时间中的至少一个 数据。

    MEMORY SYSTEM AND DATA WRITING METHOD
    37.
    发明申请
    MEMORY SYSTEM AND DATA WRITING METHOD 失效
    记忆系统和数据写入方法

    公开(公告)号：US20080043534A1

    公开(公告)日：2008-02-21

    申请号：US11846334

    申请日：2007-08-28

    申请人： Kazuya Kawamoto ,  Yoshiyuki Tanaka ,  Hiroshi Sukegawa

    发明人： Kazuya Kawamoto ,  Yoshiyuki Tanaka ,  Hiroshi Sukegawa

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/10

    摘要： A data writing method is disclosed. In a memory system comprising a NAND flash memory and a controller which controls the memory, the memory system storing data provided from a host to the NAND flash memory, the data writing method comprises a steps of specifying a column address in which a column failure which has occurred in the NAND flash memory by the controller, and a step of, during writing into the NAND flash memory, writing data of a first logic level into a memory cell which corresponds to the specified column address regardless of write data provided from the controller.

    摘要翻译： 公开了一种数据写入方法。 在包括NAND闪速存储器和控制存储器的控制器的存储器系统中，存储器系统存储从主机向NAND闪速存储器提供的数据，该数据写入方法包括以下步骤：指定列地址，其中列失败 已经在控制器的NAND闪速存储器中发生了这种情况，并且在写入NAND闪速存储器期间，将第一逻辑电平的数据写入到与指定的列地址对应的存储单元中，而不管从控制器提供的写数据如何 。

    Person identification device and person identification method
    38.
    发明申请
    Person identification device and person identification method 有权
    人员识别装置和人身识别方法

    公开(公告)号：US20070189585A1

    公开(公告)日：2007-08-16

    申请号：US11705795

    申请日：2007-02-14

    申请人： Hiroshi Sukegawa ,  Makoto Shimizu

    发明人： Hiroshi Sukegawa ,  Makoto Shimizu

    IPC分类号： G06K9/00

    CPC分类号： G07C9/00158 ,  G06K9/00221 ,  G06K9/00885

    摘要： A person identification device obtains information including biometric information of a person, detects the biometric information of at least one person from the obtained information, collates each detected biometric information with the biometric information of at least one registrant associated with group information and stored in a storage unit to thereby identify the person having the biometric information detected from the obtained information, classifies a plurality of successively identified persons into group candidates based on predetermined conditions, divides the persons of the group candidates into groups based on the group information of each person stored in the storage unit, and outputs a grouping result to an external device.

    摘要翻译： 个人识别装置获取包括人的生物信息的信息，从获得的信息中检测至少一个人的生物信息，将每个检测到的生物体信息与至少一个与组信息相关联的注册者的生物特征信息进行核对并存储在存储器 单元，从而根据所获得的信息识别具有检测到的生物特征信息的人，基于预定条件将多个连续识别的人分类为群体候选，基于存储在每个人中的每个人的组信息将群体候选人的人员分组 存储单元，并将分组结果输出到外部设备。

    Semiconductor memory device which prevents destruction of data
    39.
    发明申请
    Semiconductor memory device which prevents destruction of data 有权
    防止数据破坏的半导体存储器件

    公开(公告)号：US20070035997A1

    公开(公告)日：2007-02-15

    申请号：US11498142

    申请日：2006-08-03

    申请人： Noboru Shibata ,  Hiroshi Sukegawa

    发明人： Noboru Shibata ,  Hiroshi Sukegawa

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C16/0483

    摘要： A plurality of memory cells each storing n values (n is a natural number which is not smaller than 3) are arranged in a matrix form in a memory cell array, and each memory cell is connected with a word line and a bit line. Each memory cell stores the n-valued data by a first write operation and a second write operation. A read section sets a potential of a word line, and reads data from a memory cell in the memory cell array. If data read by the read section and written in the second write operation includes an uncorrectable error, a control section changes a potential of a word line supplied to the read section when reading data written in the first write operation.

    摘要翻译： 每个存储n个值的多个存储单元（n是不小于3的自然数）以矩阵形式布置在存储单元阵列中，并且每个存储单元与字线和位线连接。 每个存储单元通过第一写操作和第二写操作来存储n值数据。 读取部分设置字线的电位，并从存储器单元阵列中的存储单元读取数据。 如果由读取部分读取并写入第二写入操作的数据包括不可校正的错误，则当读取在第一写入操作中写入的数据时，控制部分改变提供给读取部分的字线的电位。