公开(公告)号：US6124621A

公开(公告)日：2000-09-26

申请号：US314528

申请日：1999-05-19

Applicant: Yung-Chang Lin ,  Jih-Wen Chou ,  Tung-Po Chen

Inventor： Yung-Chang Lin ,  Jih-Wen Chou ,  Tung-Po Chen

IPC: H01L21/336 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L29/6659 ,  H01L29/6656 ,  Y10S257/90 ,  Y10S257/915

Abstract: A structure of a spacer in a semiconductor device is disclosed. Firstly, a gate without a spacer is provided on a substrate. A first insulating layer is formed on the sidewall of the gate. After a lightly doped drain is subsequently achieved in the substrate, a second insulating layer is formed on the first spacer. The process following this embodiment described above is to form a heavily doped drain in the substrate, then the whole MOSFET fabrication is completed. The present invention can enhance the stability of resistance of the gate and reduce pollution of the machine. Therefore, quality and efficiency of the fabrication of MOSFET will be enhanced.

Abstract translation: 公开了半导体器件中的间隔物的结构。 首先，在衬底上设置没有间隔物的栅极。 第一绝缘层形成在栅极的侧壁上。 在衬底中随后实现轻掺杂漏极之后，在第一间隔物上形成第二绝缘层。 按照上述实施例描述的工艺是在衬底中形成重掺杂漏极，然后完成整个MOSFET制造。 本发明可以提高门的电阻的稳定性并减少机器的污染。 因此，MOSFET的制造的质量和效率将得到提高。

公开(公告)号：US6060349A

公开(公告)日：2000-05-09

申请号：US152449

申请日：1998-09-14

Applicant: Tzu-Min Peng ,  Keh-Ching Huang ,  Tung-Po Chen ,  Tz-Guei Jung

Inventor： Tzu-Min Peng ,  Keh-Ching Huang ,  Tung-Po Chen ,  Tz-Guei Jung

IPC: H01L21/8242

CPC classification number: H01L27/10844 ,  H01L27/10852

Abstract: A planarization method used in fabricating an embedded dynamic random access memory (DRAM). After a number of metal-oxide semiconductor (MOS) transistors and a number of capacitors are formed on a semiconductor substrate, a first inter-layer di-electric (ILD) layer is formed over the substrate. The embedded DRAM is divided into a memory region and a logic region. Next, planarization is performed. A dummy metal layer is formed and coupled to an interchangeable source/drain region of the MOS transistor in the logic region. Then a second ILD layer is formed over the logic region to compensate difference in height between the logic region and the memory region. Then, a via hole/plug is formed in the logic region to extend the first metal layer. A second metal layer with required contact window/plugs is formed over the substrate.

Abstract translation: 用于制造嵌入式动态随机存取存储器（DRAM）的平面化方法。 在半导体衬底上形成多个金属氧化物半导体（MOS）晶体管和多个电容器之后，在衬底上形成第一层间二电极（ILD）层。 嵌入式DRAM被分成存储区域和逻辑区域。 接下来，进行平坦化。 形成虚设的金属层并与逻辑区域中的MOS晶体管的可互换的源/漏区耦合。 然后在逻辑区域上形成第二ILD层以补偿逻辑区域和存储区域之间的高度差异。 然后，在逻辑区域中形成通孔/插头以延伸第一金属层。 在衬底上形成具有所需接触窗/插塞的第二金属层。

公开(公告)号：US6022795A

公开(公告)日：2000-02-08

申请号：US73861

申请日：1998-05-07

Applicant: Tung-Po Chen ,  Hong-Tsz Pan ,  Wen-Yi Hsieh

Inventor： Tung-Po Chen ,  Hong-Tsz Pan ,  Wen-Yi Hsieh

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/3205

CPC classification number: H01L29/665 ,  H01L21/28052 ,  H01L21/28518

Abstract: A method of making a semiconductor device including a MOS transistor provides an insulator formed on a semiconductor substrate and a gate electrode formed on the insulator. Source/drain regions are formed within the substrate on either side of the gate electrode. A layer of titanium is sputtered onto the semiconductor device, and a layer of titanium nitride is direct sputtered over the titanium layer using a titanium nitride target. The device is annealed at a first temperature to form a structure including titanium silicide on the polysilicon electrode, titanium silicide on the surface of the source/drain regions, unreacted titanium over the silicide regions, and titanium nitride over the unreacted metal. The unreacted titanium and titanium nitride are removed from the structure, and the structure is annealed at a higher temperature than the first temperature to form a lower resistivity titanium silicide.

公开(公告)号：US5893751A

公开(公告)日：1999-04-13

申请号：US736939

申请日：1996-10-25

Applicant: Jason Jenq ,  Tung-Po Chen

Inventor： Jason Jenq ,  Tung-Po Chen

IPC: H01L21/285 ,  H01L21/44

CPC classification number: H01L21/28518

Abstract: An improved self-aligned silicide manufacturing method in which prior to the formation of a heat resistant metallic layer on top of a silicon substrate, a treatment of exposed surfaces of a gate terminal and source/drain diffusion regions is performed to increase surface roughness enabling an increase in crystallization nucleus number, as well as lowering crystallization temperature.

Abstract translation: 一种改进的自对准硅化物制造方法，其中在硅衬底顶部形成耐热金属层之前，执行对栅极端子和源极/漏极扩散区域的暴露表面的处理，以增加表面粗糙度，从而能够 结晶核数增加，结晶温度降低。