公开(公告)号：US20080294881A1

公开(公告)日：2008-11-27

申请号：US11753005

申请日：2007-05-24

申请人： Wen-Tzer Thomas Chen ,  Venkat Rajeev Indukuru ,  Alexander Erik Mericas ,  Mysore Sathyanarayana Srinivas

发明人： Wen-Tzer Thomas Chen ,  Venkat Rajeev Indukuru ,  Alexander Erik Mericas ,  Mysore Sathyanarayana Srinivas

IPC分类号： G06F11/34

CPC分类号： G06F11/3409 ,  G06F11/3471 ,  G06F11/3476 ,  G06F2201/86 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2201/885

摘要： An information handling system includes a processor that executes multiple instructions or instruction threads within a software application program. The information handling system includes operating system software that manages processor system hardware and software in a multi-tasking environment. In one embodiment, the operating system manages instruction completion stall analysis software to determine the cause or causes of instruction stalls. In another embodiment, the stall analysis software cooperates with the operating system software to store instruction completion stall event data on a per instruction basis while the application program executes. The operating system software may cooperate with the stall analysis software to store instruction completion stall data in memory for later manipulation by system users or other software.

摘要翻译： 信息处理系统包括在软件应用程序内执行多个指令或指令线程的处理器。 信息处理系统包括在多任务环境中管理处理器系统硬件和软件的操作系统软件。 在一个实施例中，操作系统管理指令完成失速分析软件以确定指令停顿的原因或原因。 在另一个实施例中，失速分析软件与操作系统软件配合，以在应用程序执行时以每个指令为基础存储指令完成失速事件数据。 操作系统软件可以与失速分析软件配合以将指令完成失速数据存储在存储器中以供系统用户或其他软件稍后操作。

公开(公告)号：US07437618B2

公开(公告)日：2008-10-14

申请号：US11055977

申请日：2005-02-11

申请人： Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

发明人： Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

IPC分类号： G06F11/00

CPC分类号： G06F11/2268 ,  G06F11/3476 ,  G06F11/348

摘要： A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a memory controller that controls a system memory. A particular size of the system memory is determined that is needed for storing trace data. A hardware trace facility requests, dynamically after the data processing system has completed booting, the particular size of the system memory to be allocated to the hardware trace facility for storing trace data that is captured by the hardware trace facility. The firmware selects particular locations within the system memory. All of the particular locations together are the particular size. The firmware allocates the particular locations for use exclusively by the hardware trace facility.

摘要翻译： 在处理器中公开了一种方法，装置和计算机程序产品，用于在运行时期间动态地为存储器内硬件跟踪分配存储器。 处理器包含在数据处理系统中。 处理器包括使用系统总线耦合在一起的多个处理单元。 处理单元包括控制系统存储器的存储器控​​制器。 确定存储跟踪数据所需的特定大小的系统存储器。 硬件跟踪设施在数据处理系统完成启动之后动态地请求要分配给硬件跟踪设备的系统内存的特定大小，用于存储由硬件跟踪设备捕获的跟踪数据。 固件选择系统内存中的特定位置。 所有特定位置在一起是特定的尺寸。 固件分配由硬件跟踪设备专门使用的特定位置。

公开(公告)号：US07421619B2

公开(公告)日：2008-09-02

申请号：US11055821

申请日：2005-02-11

申请人： Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

发明人： Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

IPC分类号： G06F11/00

CPC分类号： G06F11/2268 ,  G06F11/348

摘要： A method, apparatus, and computer program product are disclosed for performing in-memory hardware tracing in a processor using an existing system bus. The processor includes multiple processing units that are coupled together utilizing the system bus. The processing units include a memory controller that controls a system memory. Information is transmitted among the processing units utilizing the system bus. The information is formatted according to a standard system bus protocol. Hardware trace data is captured utilizing a hardware trace facility that is coupled directly to the system bus. The system bus is utilized for transmitting the hardware trace data to the memory controller for storage in the system memory. The memory controller is coupled directly to the system bus. The hardware trace data is formatted according to the standard system bus protocol for transmission via the system bus.

摘要翻译： 公开了一种用于使用现有系统总线在处理器中执行存储器内硬件跟踪的方法，装置和计算机程序产品。 处理器包括利用系统总线耦合在一起的多个处理单元。 处理单元包括控制系统存储器的存储器控​​制器。 利用系统总线在处理单元之间传送信息。 信息根据标准系统总线协议进行格式化。 使用直接耦合到系统总线的硬件跟踪功能来捕获硬件跟踪数据。 系统总线用于将硬件跟踪数据发送到存储器控制器以存储在系统存储器中。 存储器控制器直接耦合到系统总线。 硬件跟踪数据根据标准系统总线协议进行格式化，以便通过系统总线进行传输。

公开(公告)号：US06895399B2

公开(公告)日：2005-05-17

申请号：US09951959

申请日：2001-09-13

申请人： Alexander Erik Mericas

发明人： Alexander Erik Mericas

IPC分类号： G06F9/50 ,  G06F17/00

CPC分类号： G06F9/5011 ,  G06F2209/507

摘要： A data processing system, method, and product are disclosed for dynamically allocating resources for multiple, different types of events that occur within a microprocessor. Multiple, different unallocated resources are provided. One of these unallocated resources are allocated only in response to a first occurrence of an event that is one of the different types of events. Thus, resources remain unallocated until a first occurrence of events for which resources are then allocated.

摘要翻译： 公开了一种数据处理系统，方法和产品，用于为在微处理器内发生的多种不同类型的事件动态分配资源。 提供了多种不同的未分配资源。 这些未分配资源中的一个仅在响应于作为不同类型的事件之一的事件的第一次出现时被分配。 因此，资源保持未分配，直到首先发生资源然后被分配的事件。

公开(公告)号：US06718403B2

公开(公告)日：2004-04-06

申请号：US09734116

申请日：2000-12-11

申请人： Joel Roger Davidson ,  Judith E. K. Laurens ,  Alexander Erik Mericas

发明人： Joel Roger Davidson ,  Judith E. K. Laurens ,  Alexander Erik Mericas

IPC分类号： G06E300

CPC分类号： G06F13/4217 ,  G06F11/3409 ,  G06F11/3466 ,  G06F11/349 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

摘要： A microprocessor including a performance monitor unit is disclosed. The performance monitor unit includes a set of performance monitor counters and a corresponding set of control circuits and programmable control registers. The performance monitor unit receives a first set of event signals from functional units of the processor. Each of the first set of events is routed directly from the appropriate functional unit to the performance monitor unit. The performance monitor unit further receives at least a second set of event signals. In one embodiment, the second set of event signals is received via a performance monitor bus of the processor. The performance monitor bus is typically a shared bus that may receive signals from any of the functional units of the processor. The functional units may include multiplexing circuitry that determines which of the functional units has mastership of the shared bus. Whereas the performance monitor unit is typically capable of monitoring the direct event signals in any of its counters, the indirect event signals may be selectively routed to the counters. The shared bus may be divided into sub-groups or byte lanes where the byte lanes are selectively routed to the set of performance monitor counters. The state of a control register may determine the event that is monitored in the corresponding counter. In one embodiment, the control register provides a set of signals that are connected to the select inputs of one or more multiplexers. The multiplexers receive multiple events signals and, based on the state of their select signals, route one of the received event signals to the corresponding performance monitor counter. Specified states of the select signals may result in the disabling of the corresponding counter or enabling the counter to count system clock cycles rather than any performance event.

摘要翻译： 公开了一种包括性能监视器单元的微处理器。 性能监视器单元包括一组性能监视计数器和一组相应的控制电路和可编程控制寄存器。 性能监视器单元从处理器的功能单元接收第一组事件信号。 第一组事件中的每一个直接从适当的功能单元路由到性能监视器单元。 性能监视器单元进一步接收至少第二组事件信号。 在一个实施例中，经由处理器的性能监视总线接收第二组事件信号。 性能监视器总线通常是可以从处理器的任何功能单元接收信号的共享总线。 功能单元可以包括复用电路，其确定哪个功能单元具有共享总线的掌握。 而性能监视器单元通常能够监视任何其计数器中的直接事件信号，间接事件信号可被选择性地路由到计数器。 共享总线可以被划分成子组或字节通道，其中字节通道被选择性地路由到一组性能监视计数器。 控制寄存器的状态可以确定在相应计数器中监视的事件。 在一个实施例中，控制寄存器提供连接到一个或多个多路复用器的选择输入的一组信号。 多路复用器接收多个事件信号，并且基于其选择信号的状态，将接收的事件信号中的一个路由到相应的性能监视计数器。 选择信号的指定状态可能导致禁用相应的计数器或使计数器能够对系统时钟周期进行计数，而不是任何性能事件。

公开(公告)号：US06415378B1

公开(公告)日：2002-07-02

申请号：US09343359

申请日：1999-06-30

申请人： Joel Roger Davidson ,  Judith K. Laurens ,  Alexander Erik Mericas ,  Kevin F. Reick ,  Joel M. Tendler

发明人： Joel Roger Davidson ,  Judith K. Laurens ,  Alexander Erik Mericas ,  Kevin F. Reick ,  Joel M. Tendler

IPC分类号： G06F1100

CPC分类号： G06F11/3466

摘要： A method and system for debugging the execution of an instruction within an instruction pipeline is provided. A processor in a data processing system contains instruction pipeline units. An instruction may be tagged, and in response to an instruction pipeline unit completing its processing of the tagged instruction, a stage completion signal is asserted. An execution monitor external to the pipelined processor monitors the stage completion signals during the execution of the tagged instruction. The execution monitor may be a logic analyzer that displays the stage completion signals in real-time on a display device of the execution monitor. An instruction to be tagged may be selected based upon an instruction selection rule, such as the address of the instruction.

摘要翻译： 提供了一种用于调试指令管线内的指令执行的方法和系统。 数据处理系统中的处理器包含指令流水线单元。 指令可以被标记，并且响应于指令流水线单元完成其对带标签的指令的处理，声明级完成信号。 流水线处理器外部的执行监视器在执行标记指令期间监视阶段完成信号。 执行监视器可以是在执行监视器的显示装置上实时显示级完成信号的逻辑分析器。 可以基于诸如指令的地址的指令选择规则来选择要被标记的指令。

公开(公告)号：US08234484B2

公开(公告)日：2012-07-31

申请号：US12099944

申请日：2008-04-09

申请人： Venkat Rajeev Indukuru ,  Alexander Erik Mericas

发明人： Venkat Rajeev Indukuru ,  Alexander Erik Mericas

IPC分类号： G06F9/30

CPC分类号： G06F9/3844 ,  G06F9/3802 ,  G06F9/3853 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3885 ,  G06F11/3466 ,  G06F11/348 ,  G06F2201/86

摘要： A method, computer program product, and data processing system for collecting metrics regarding completion stalls in an out-of-order superscalar processor with branch prediction is disclosed. A preferred embodiment of the present invention selectively samples particular instructions (or classes of instructions). Each selected instruction, as it passes through the processor datapath, is marked (tagged) for monitoring by a performance monitoring unit. The progress of marked instructions is monitored by the performance monitoring unit, and various stall counters are triggered by the progress of the marked instructions and the instruction groups they form a part of. The stall counters count cycles to give an indication of when certain delays associated with particular instructions occur and how serious the delays are.

摘要翻译： 公开了一种用于在具有分支预测的无序超标量处理器中收集关于完成停顿的度量的方法，计算机程序产品和数据处理系统。 本发明的优选实施例有选择地对特定指令（或指令类别）进行采样。 每个选定的指令在通过处理器数据路径时被标记（标记），用于由性能监视单元监视。 标记指令的进度由性能监控单元进行监控，各种失速计数器由标记指令和指令组的进度触发。 停顿计数器计数周期，以指示何时发生与特定指令相关的某些延迟以及延迟的严重程度。

公开(公告)号：US07617385B2

公开(公告)日：2009-11-10

申请号：US11675112

申请日：2007-02-15

申请人： Venkat Rajeev Indukuru ,  Alexander Erik Mericas

发明人： Venkat Rajeev Indukuru ,  Alexander Erik Mericas

IPC分类号： G06F11/28

CPC分类号： G06F9/3867 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F11/3423 ,  G06F11/3466 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

摘要： A computer implemented method, apparatus, and computer program product for monitoring execution of instructions in an instruction pipeline. The process identifies a number of stall cycles for a group of instructions to complete execution. The process retrieves a deterministic latency pattern corresponding to the group of instructions. The process compares the number of stall cycles to the deterministic execution latency pattern. The process identifies the instruction as a dependent instruction in response to a determination that an instruction in the group of instructions completed a deterministic number of cycles after an antecedent instruction completed.

摘要翻译： 一种计算机实现的方法，装置和计算机程序产品，用于监视指令流水线中的指令的执行。 该过程识别一组完成执行的指令的停顿周期数。 该过程检索对应于该组指令的确定性延迟模式。 该过程将停顿周期数与确定性执行延迟模式进行比较。 响应于确定指令组中的指令在前提指令完成之后完成确定性循环次数，该过程将该指令标识为依赖指令。

公开(公告)号：US20090031173A1

公开(公告)日：2009-01-29

申请号：US12206967

申请日：2008-09-09

申请人： Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

发明人： Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

IPC分类号： G06F11/00 ,  G06F11/07

CPC分类号： G06F11/2268 ,  G06F11/3476 ,  G06F11/348

摘要： A method, apparatus, and computer program product are disclosed in a processor for dynamically, during runtime, allocating memory for in-memory hardware tracing. The processor is included within a data processing system. The processor includes multiple processing units that are coupled together utilizing a system bus. The processing units include a memory controller that controls a system memory. A particular size of the system memory is determined that is needed for storing trace data. A hardware trace facility requests, dynamically after the data processing system has completed booting, the particular size of the system memory to be allocated to the hardware trace facility for storing trace data that is captured by the hardware trace facility. The firmware selects particular locations within the system memory. All of the particular locations together are the particular size. The firmware allocates the particular locations for use exclusively by the hardware trace facility.

摘要翻译： 在处理器中公开了一种方法，装置和计算机程序产品，用于在运行时期间动态地为存储器内硬件跟踪分配存储器。 处理器包含在数据处理系统中。 处理器包括使用系统总线耦合在一起的多个处理单元。 处理单元包括控制系统存储器的存储器控​​制器。 确定存储跟踪数据所需的特定大小的系统存储器。 硬件跟踪设施在数据处理系统完成启动之后动态地请求要分配给硬件跟踪设备的系统内存的特定大小，用于存储由硬件跟踪设备捕获的跟踪数据。 固件选择系统内存中的特定位置。 所有特定位置在一起是特定的尺寸。 固件分配由硬件跟踪设备专门使用的特定位置。

公开(公告)号：US07437617B2

公开(公告)日：2008-10-14

申请号：US11055845

申请日：2005-02-11

申请人： Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

发明人： Ra'ed Mohammad Al-Omari ,  Alexander Erik Mericas ,  William John Starke

IPC分类号： G06F11/00

CPC分类号： G06F11/2268 ,  G06F11/348

摘要： A method, apparatus, and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.

摘要翻译： 公开了一种方法，装置和计算机程序产品，用于在处理器中使用可编程可变数量的共享存储器写缓冲器在跟踪处理和非跟踪处理之间共享存储器控制器。 硬件跟踪设备捕获处理器中的硬件跟踪数据。 硬件跟踪工具包含在处理器内。 使用系统总线将硬件跟踪数据传输到系统存储器。 系统内存包含在系统中。 当将硬件跟踪数据发送到系统总线时，系统总线能够被包括在处理节点中的处理单元利用。 系统内存的一部分用于存储跟踪数据。 系统存储器能够被处理节点除硬件跟踪设备之外的处理单元访问，同时系统存储器的一部分用于存储跟踪数据。