公开(公告)号：US07365018B2

公开(公告)日：2008-04-29

申请号：US11319895

申请日：2005-12-28

申请人： Masaaki Higashitani ,  Tuan Pham ,  Masayuki Ichige ,  Koji Hashimoto ,  Satoshi Tanaka ,  Kikuko Sugimae

发明人： Masaaki Higashitani ,  Tuan Pham ,  Masayuki Ichige ,  Koji Hashimoto ,  Satoshi Tanaka ,  Kikuko Sugimae

IPC分类号： H01L21/302

CPC分类号： H01L21/28123 ,  H01L21/32139 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques. In one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3 F or 5 F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F, and select gates of width 3 F spaced apart by 3 F or 5 F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.

摘要翻译： 使用现有的光刻技术制造具有例如45-55nm或更小的通道长度的存储元件的非易失性存储器件。 在一种方法中，第一和第二光掩模的图案被转移到相同的光致抗蚀剂层。 第一光掩模可以具有例如由特征尺寸F间隔开的具有给定特征尺寸F的开口。 第二光掩模具有一个开口，其尺寸被设计成产生期望的选择性间隙，例如3F或5F。第三光掩模用于在选择栅极结构上的第二光致抗蚀剂层中提供保护部分。 最终结构具有间隔开距离F的宽度为F的存储元件，并且以3F或5F隔开的宽度3F的选择栅极。另一种方法是将三个光掩模的图案转移到相应的光致抗蚀剂层，以形成 类似的最终结构。

公开(公告)号：US20060077702A1

公开(公告)日：2006-04-13

申请号：US11125274

申请日：2005-05-10

申请人： Kikuko Sugimae ,  Satoshi Tanaka ,  Koji Hashimoto ,  Masayuki Ichige

发明人： Kikuko Sugimae ,  Satoshi Tanaka ,  Koji Hashimoto ,  Masayuki Ichige

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C16/0408 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531

摘要： Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AAi, AAi+1, . . . , AAn, which extend on a memory cell array along the column length; a plurality of word line patterns WL1, WL2, . . . , extend along the row length and are non-uniformly arranged; a plurality of select gate line patterns SG1, SG2, . . . , are arranged parallel to the plurality of word line patterns; borderless contacts are formed near the ends of the word line patterns on the memory cell array, and are in contact with part of an interconnect extended from the end of the memory cell array, but are not in contact with interconnects adjacent to that interconnect; and bit line contacts are formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.

摘要翻译： 用于字线的无边界触点或通过位线的触点使用互连图案形成，其中一部分被去除。 半导体存储器包括：多个有源区域AA 1，A 2，...，N 1，...， 。 。 ，沿着列长延伸在存储单元阵列上的AA 多个字线图形WL 1，WL 2，...。 。 。 沿着行长延伸并且不均匀地布置; 多个选择栅极线图案SG 1，SG 2，...。 。 。 被平行于所述多个字线图形排列; 在存储单元阵列上的字线图案的端部附近形成无边界触点，并且与从存储单元阵列的端部延伸的互连部分接触，但不与与该互连件相邻的互连件接触; 并且通过去除多个字线图案的一部分而提供的接触形成区域内形成位线接触，并通过双重曝光选择栅极线图案。

公开(公告)号：US20090154214A1

公开(公告)日：2009-06-18

申请号：US12370638

申请日：2009-02-13

申请人： Kikuko Sugimae ,  Satoshi Tanaka ,  Koji Hashimoto ,  Masayuki Ichige

发明人： Kikuko Sugimae ,  Satoshi Tanaka ,  Koji Hashimoto ,  Masayuki Ichige

IPC分类号： G11C5/02 ,  G11C5/06

CPC分类号： G11C5/063 ,  G11C16/0408 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531

摘要： Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AAi, AAi, . . . , AAn, which extend on a memory cell array along the column length; a plurality of word line patterns WL1, WL2, . . . , extend along the row length and are non-uniformly arranged; a plurality of select gate line patterns SG1, SG2, . . . , are arranged parallel to the plurality of word line patterns; borderless contacts are formed near the ends of the word line patterns on the memory cell array, and are in contact with part of an interconnect extended from the end of the memory cell array, but are not in contact with interconnects adjacent to that interconnect; and bit line contacts are formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.

摘要翻译： 用于字线的无边界触点或通过位线的触点使用互连图案形成，其中一部分被去除。 半导体存储器包括：多个有源区域AAi，AAi，...。 。 。 ，AAn，其沿着列长延伸在存储单元阵列上; 多个字线图案WL1，WL2，...。 。 。 沿着行长延伸并且不均匀地布置; 多个选择栅极线图案SG1，SG2，...。 。 。 被平行于所述多个字线图形排列; 在存储单元阵列上的字线图案的端部附近形成无边界触点，并且与从存储单元阵列的端部延伸的互连部分接触，但不与与该互连件相邻的互连件接触; 并且通过去除多个字线图案的一部分而提供的接触形成区域内形成位线接触，并通过双重曝光选择栅极线图案。

公开(公告)号：US20080153301A1

公开(公告)日：2008-06-26

申请号：US12010933

申请日：2008-01-31

申请人： Satoshi Tanaka ,  Koji Hashimoto

发明人： Satoshi Tanaka ,  Koji Hashimoto

IPC分类号： H01L21/311

CPC分类号： H01L21/0274 ,  G03F1/70 ,  G06F17/5068 ,  H01L21/31144 ,  H01L21/32139

摘要： A method of generating mask data, for a set of masks used to transfer a pattern for delineating a circuit pattern of a semiconductor integrated circuit, includes preparing design data having a design pattern corresponding to the pattern to be transferred on a semiconductor substrate; generating resized data by enlarging the design data by a resizing quantity; generating first mask data by filling a space area having a space width of a space quantity or less of the resized data; and generating second mask data, to be aligned with the first mask data, having a window portion for selectively exposing an area determined by enlarging the space area by the resizing quantity.

公开(公告)号：US20070148973A1

公开(公告)日：2007-06-28

申请号：US11319895

申请日：2005-12-28

申请人： Masaaki Higashitani ,  Tuan Pham ,  Masayuki Ichige ,  Koji Hashimoto ,  Satoshi Tanaka ,  Kikuko Sugimae

发明人： Masaaki Higashitani ,  Tuan Pham ,  Masayuki Ichige ,  Koji Hashimoto ,  Satoshi Tanaka ,  Kikuko Sugimae

IPC分类号： H01L21/302 ,  B44C1/22 ,  H01L21/461

CPC分类号： H01L21/28123 ,  H01L21/32139 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques. In one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3 F or 5 F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F, and select gates of width 3 F spaced apart by 3 F or 5 F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.

摘要翻译： 使用现有的光刻技术制造具有例如45-55nm或更小的通道长度的存储元件的非易失性存储器件。 在一种方法中，第一和第二光掩模的图案被转移到相同的光致抗蚀剂层。 第一光掩模可以具有例如由特征尺寸F间隔开的具有给定特征尺寸F的开口。 第二光掩模具有一个开口，其尺寸被设计成产生期望的选择性间隙，例如3F或5F。第三光掩模用于在选择栅极结构上的第二光致抗蚀剂层中提供保护部分。 最终结构具有间隔开距离F的宽度为F的存储元件，并且以3F或5F隔开的宽度3F的选择栅极。另一种方法是将三个光掩模的图案转移到相应的光致抗蚀剂层，以产生 类似的最终结构。

公开(公告)号：US6004701A

公开(公告)日：1999-12-21

申请号：US46794

申请日：1998-03-24

申请人： Taiga Uno ,  Kiyomi Koyama ,  Kazuko Yamamoto ,  Satoshi Tanaka ,  Sachiko Kobayashi ,  Koji Hashimoto

发明人： Taiga Uno ,  Kiyomi Koyama ,  Kazuko Yamamoto ,  Satoshi Tanaka ,  Sachiko Kobayashi ,  Koji Hashimoto

IPC分类号： G03F1/30 ,  G03F1/68 ,  H01L21/027 ,  G03F9/00 ,  G06F17/50

CPC分类号： G03F1/30

摘要： In a Levenson photomask design method of partially forming a plurality of opening patterns for passing incident light in a light-shielding film for shielding the incident light, and arranging, on some patterns, phase shifters, line segment pairs of different patterns which are adjacent to each other within a predetermined distance R are extracted in units of line segments obtained by dividing the patterns. A pattern within a predetermined distance S from the central point of the opposite region of a line segment pair of interest in a direction perpendicular to the line segments is obtained. The obtained pattern is subjected to a process simulation to obtain resolution easiness representing the easiness in resolving the adjacent patterns. On the basis of the resolution easiness obtained for the adjacent pattern pair within the distance R, a phase shifter is arranged in ascending order of resolution easiness to give a phase difference. Resolution suitable for the exposure condition used can be obtained by a simple method. When the shifter arrangement is determined in consideration of the resolution easiness, a high-resolution shifter arrangement can be realized for a Levenson phase shift mask.

摘要翻译： 在莱文森光掩模设计方法中，部分地形成用于使入射光入射到遮光膜中的入射光的多个开口图案，用于屏蔽入射光，并且在某些图案上布置移相器，与不同图案相邻的线段对 以规定的距离R为单位，以通过划分图案而得到的线段为单位提取。 获得与垂直于线段的方向相关的线段对的相对区域的中心点的预定距离S内的图案。 对所获得的图案进行处理模拟以获得表示分辨相邻图案的容易性的分辨率容易度。 基于在距离R内对相邻图案对获得的分辨率容易度，移位器按分辨率的顺序排列顺序排列以给出相位差。 可以通过简单的方法获得适合于所使用的曝光条件的分辨率。 考虑到分辨率容易度来确定移位器装置时，可以实现对莱文森相移掩模的高分辨率移位器装置。

公开(公告)号：US08312396B2

公开(公告)日：2012-11-13

申请号：US13289099

申请日：2011-11-04

申请人： Satoshi Tanaka ,  Koji Hashimoto

发明人： Satoshi Tanaka ,  Koji Hashimoto

IPC分类号： G06F17/50

CPC分类号： H01L21/0274 ,  G03F1/70 ,  G06F17/5068 ,  H01L21/31144 ,  H01L21/32139

摘要： A method of generating mask data, for a set of masks used to transfer a pattern for delineating a circuit pattern of a semiconductor integrated circuit, includes preparing design data having a design pattern corresponding to the pattern to be transferred on a semiconductor substrate; generating resized data by enlarging the design data by a resizing quantity; generating first mask data by filling a space area having a space width of a space quantity or less of the resized data; and generating second mask data, to be aligned with the first mask data, having a window portion for selectively exposing an area determined by enlarging the space area by the resizing quantity.

摘要翻译： 一种用于生成用于传送用于描绘半导体集成电路的电路图案的图案的掩模组的掩模数据的方法，包括：准备具有与要在半导体衬底上传送的图案相对应的设计图案的设计数据; 通过调整大小的数量扩大设计数据来生成调整大小的数据; 通过填充具有空间大小的空间宽度的空间区域来生成第一掩模数据; 以及生成与所述第一掩模数据对准的第二掩模数据，所述第二掩模数据具有窗口部分，用于通过所述调整大小量选择性地暴露由所述空间区域扩大所确定的区域。

公开(公告)号：US08742529B2

公开(公告)日：2014-06-03

申请号：US13332665

申请日：2011-12-21

申请人： Kikuko Sugimae ,  Satoshi Tanaka ,  Koji Hashimoto ,  Masayuki Ichige

发明人： Kikuko Sugimae ,  Satoshi Tanaka ,  Koji Hashimoto ,  Masayuki Ichige

IPC分类号： H01L27/146

CPC分类号： G11C5/063 ,  G11C16/0408 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531

摘要： A semiconductor memory includes: a plurality of active regions AAi, AAi−1, . . . , AAn, which extend on a memory cell array along the column length; a plurality of non-uniformly arranged word line patterns WL1, WL2, . . . , extending along the row length; a plurality of select gate line patterns SG1, SG2, . . . , arranged parallel to the plurality of word line patterns; borderless contacts formed near the ends of the word line patterns on the memory cell array, in contact with part of an interconnect extended from the end of the memory cell array, but not in contact with interconnects adjacent to that interconnect; and bit line contacts formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.

摘要翻译： 半导体存储器包括：多个有源区域AAi，AAi-1，...， 。 。 ，AAn，其沿着列长延伸在存储单元阵列上; 多个非均匀布置的字线图形WL1，WL2，...。 。 。 ，沿着行长延伸; 多个选择栅极线图案SG1，SG2，...。 。 。 ，平行于所述多个字线图形排列; 与存储单元阵列上的字线图案的端部附近形成无边界的触点，与从存储单元阵列的端部延伸但不与该互连相邻的互连件接触的互连部分接触; 以及形成在通过去除多个字线图案的一部分而提供的接触形成区域内的位线接触，并且通过双曝光选择栅极线图案。

公开(公告)号：US20120119304A1

公开(公告)日：2012-05-17

申请号：US13332665

申请日：2011-12-21

申请人： Kikuko SUGIMAE ,  Satoshi Tanaka ,  Koji Hashimoto ,  Masayuki Ichige

发明人： Kikuko SUGIMAE ,  Satoshi Tanaka ,  Koji Hashimoto ,  Masayuki Ichige

IPC分类号： H01L27/088

CPC分类号： G11C5/063 ,  G11C16/0408 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531

摘要： A semiconductor memory includes: a plurality of active regions AAi, AAi−1, . . . , AAn, which extend on a memory cell array along the column length; a plurality of non-uniformly arranged word line patterns WL1, WL2, . . . , extending along the row length; a plurality of select gate line patterns SG1, SG2, . . . , arranged parallel to the plurality of word line patterns; borderless contacts formed near the ends of the word line patterns on the memory cell array, in contact with part of an interconnect extended from the end of the memory cell array, but not in contact with interconnects adjacent to that interconnect; and bit line contacts formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.

摘要翻译： 半导体存储器包括：多个有源区域AAi，AAi-1，...， 。 。 ，AAn，其沿着列长延伸在存储单元阵列上; 多个非均匀布置的字线图形WL1，WL2，...。 。 。 ，沿着行长延伸; 多个选择栅极线图案SG1，SG2，...。 。 。 ，平行于所述多个字线图形排列; 与存储单元阵列上的字线图案的端部附近形成无边界的触点，与从存储单元阵列的端部延伸但不与该互连相邻的互连件接触的互连部分接触; 以及形成在通过去除多个字线图案的一部分而提供的接触形成区域内的位线接触，并且通过双曝光选择栅极线图案。

公开(公告)号：US07528452B2

公开(公告)日：2009-05-05

申请号：US11125274

申请日：2005-05-10

申请人： Kikuko Sugimae ,  Satoshi Tanaka ,  Koji Hashimoto ,  Masayuki Ichige

发明人： Kikuko Sugimae ,  Satoshi Tanaka ,  Koji Hashimoto ,  Masayuki Ichige

IPC分类号： H01L27/088

CPC分类号： G11C5/063 ,  G11C16/0408 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11531

摘要： Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AAi, AAi+1, . . . , AAn, which extend on a memory cell array along the column length; a plurality of word line patterns WL1, WL2, . . . , extend along the row length and are non-uniformly arranged; a plurality of select gate line patterns SG1, SG2, . . . , are arranged parallel to the plurality of word line patterns; borderless contacts are formed near the ends of the word line patterns on the memory cell array, and are in contact with part of an interconnect extended from the end of the memory cell array, but are not in contact with interconnects adjacent to that interconnect; and bit line contacts are formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.

摘要翻译： 用于字线的无边界触点或通过位线的触点使用互连图案形成，其中一部分被去除。 半导体存储器包括：多个有源区域AAi，AAi + 1，...， 。 。 ，AAn，其沿着列长延伸在存储单元阵列上; 多个字线图案WL1，WL2，...。 。 。 沿着行长延伸并且不均匀地布置; 多个选择栅极线图案SG1，SG2，...。 。 。 被平行于所述多个字线图形排列; 在存储单元阵列上的字线图案的端部附近形成无边界触点，并且与从存储单元阵列的端部延伸的互连部分接触，但不与与该互连件相邻的互连件接触; 并且通过去除多个字线图案的一部分而提供的接触形成区域内形成位线接触，并通过双重曝光选择栅极线图案。