公开(公告)号：US5827782A

公开(公告)日：1998-10-27

申请号：US657069

申请日：1996-06-03

申请人： Tsu Shih

发明人： Tsu Shih

IPC分类号： H01L21/768 ,  H01L21/469 ,  H01L21/302 ,  H01L21/465

CPC分类号： H01L21/76837

摘要： A method for forming a Spin-On-Glass (SOG) residue free Inter-Metal Dielectric (IMD) spacer layer as a substrate layer for a void free conformal insulator layer within a high aspect ratio exceedingly narrowly spaced patterned layer within an integrated circuit. First there is provided a semiconductor substrate having formed thereupon a patterned layer. The patterned layer has a first aperture formed therein. Formed upon the patterned layer and into the first aperture is a conformal Inter-Metal Dielectric (IMD) layer. The conformal Inter-Metal Dielectric (IMD) layer has a second aperture formed therein where the conformal Inter-Metal Dielectric (IMD) layer is formed into the first aperture. Formed upon the conformal Inter-Metal Dielectric (IMD) layer and filling the second aperture is a planarizing Spin-On-Glass (SOG) layer. There is then etched selectively and isotropically through a selective and isotropic etch the planarizing Spin-On-Glass (SOG) layer to leave remaining a Spin-On-Glass (SOG) layer residue within the second aperture. Finally, there is then etched non-selectively and anisotropically through a non-selective and anisotropic etch the Spin-On-Glass (SOG) layer residue and the conformal Inter-Metal Dielectric (IMD) layer to leave remaining an Inter-Metal Dielectric (IMD) spacer layer adjoining the patterned layer.

摘要翻译： 一种用于在高纵横比内的无空隙共形绝缘体层的形成用于形成无旋转玻璃（SOG）无残留金属间介电层（IMD）间隔层的方法，该集成电路内的非常窄的间隔图案层。 首先，提供在其上形成图案化层的半导体衬底。 图案化层具有形成在其中的第一孔。 形成在图案层上并且形成第一孔是共形的金属介电层（IMD）层。 共形金属介质（IMD）层具有形成在其中的第二孔，其中共形金属介电层（IMD）层形成第一孔。 形成在保形金属间电介质（IMD）层上并填充第二孔是平面化旋转玻璃（SOG）层。 然后通过选择性和各向同性蚀刻选择性地和各向同性地蚀刻平面化旋转玻璃（SOG）层，以在第二孔内留下旋转玻璃（SOG）层残留物。 最后，然后通过非选择性和各向异性蚀刻非旋转和各向异性地蚀刻旋转玻璃（SOG）层残余物和共形金属间介电层（IMD）层，留下金属间介质 IMD）间隔层。

公开(公告)号：US5654234A

公开(公告)日：1997-08-05

申请号：US638674

申请日：1996-04-29

申请人： Tsu Shih ,  Chen-Hua Douglas Yu

发明人： Tsu Shih ,  Chen-Hua Douglas Yu

IPC分类号： H01L21/285 ,  H01L21/283

CPC分类号： H01L21/28556

摘要： A method for the fabrication of an ohmic, low resistance contact to silicon is described using a CVD deposited tungsten plug provided with Ti/TiN barrier metallurgy. The method provides for a glass insulator layer deposited on the silicon. After the glass is flowed to planarize its surface, contact holes are patterned in the glass exposing the silicon substrate. The Ti/TiN barrier metallurgy is deposited by sputtering which, because of inferior edge coverage, results in a sidewall with a negative taper. Subsequent deposition of the tungsten results in a tungsten plug with an exposed void. The method taught by this invention deposits first a thin layer of tungsten whose thickness is governed by the amount of overhang caused by the tapered sidewall. An anisotropic dry etch step is then performed to achieve a vertical sidewall of tungsten. The remaining tungsten is then deposited to fill the contact opening without the occurrence of voids.

摘要翻译： 使用具有Ti / TiN屏蔽冶金的CVD沉积钨插塞来描述用于制造欧姆，低电阻接触硅的方法。 该方法提供了沉积在硅上的玻璃绝缘体层。 在玻璃流动以平坦化其表面之后，在暴露硅衬底的玻璃中图案化接触孔。 通过溅射沉积Ti / TiN屏障冶金，由于较差的边缘覆盖，导致具有负锥度的侧壁。 随后钨的沉积导致具有暴露空隙的钨插塞。 本发明教导的方法首先沉积一薄层钨，其厚度由锥形侧壁引起的悬垂量决定。 然后执行各向异性干蚀刻步骤以实现钨的垂直侧壁。 然后沉积剩余的钨以填充接触开口而不发生空隙。

公开(公告)号：US07091126B2

公开(公告)日：2006-08-15

申请号：US10422443

申请日：2003-04-24

申请人： Han-Hsin Kuo ,  Hung-Wen Su ,  Wen-Chih Chiou ,  Tsu Shih ,  Hsien-Ming Lee

发明人： Han-Hsin Kuo ,  Hung-Wen Su ,  Wen-Chih Chiou ,  Tsu Shih ,  Hsien-Ming Lee

IPC分类号： H01L21/302

CPC分类号： H01L21/76886 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/7684

摘要： An improvement in a copper damascene process is disclosed. The improvement comprises the step of projecting an electron beam on to a chemical mechanically polished material surface having copper filled etched trenches at a known angle of incidence with respect to the material surface for a known period of time, the electron beam having a beamwidth substantially covering the material surface and a known intensity.

摘要翻译： 披露了铜镶嵌工艺的改进。 该改进包括将电子束投射到具有铜填充的蚀刻沟槽的化学机械抛光的材料表面上的步骤，其具有相对于材料表面已知的入射角已知的时间段，电子束具有基本覆盖的波束宽度 材料表面和已知的强度。

公开(公告)号：US20050064629A1

公开(公告)日：2005-03-24

申请号：US10665309

申请日：2003-09-22

申请人： Chen-Hua Yu ,  Tsu Shih ,  Chung-Shi Liu ,  Shwang-Min Jeng ,  Horng-Huei Tseng

发明人： Chen-Hua Yu ,  Tsu Shih ,  Chung-Shi Liu ,  Shwang-Min Jeng ,  Horng-Huei Tseng

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76829 ,  H01L21/76834

摘要： An interconnect structure utilizing a silicon carbon-containing film as an interlayer between dielectrics. A semiconductor substrate having a conductor thereon is provided, and an insulating layer overlies the semiconductor substrate. The insulating layer has a via hole therein to expose the conductor. A conductive plug, e.g. a tungsten plug, substantially fills the via hole and electrically connects the underlying conductor. A silicon carbon-containing film and a low k dielectric layer overlie the insulating layer and the conductive plug, and have a trench therein exposing the conductive plug. A copper or copper alloy conductor substantially fills the trench.

摘要翻译： 利用含硅碳膜作为电介质之间的中间层的互连结构。 设置有其上具有导体的半导体衬底，并且绝缘层覆盖在半导体衬底上。 绝缘层在其中具有通孔以露出导体。 导电塞，例如。 钨插头基本上填充通孔并电连接下面的导体。 含硅碳膜和低k电介质层覆盖在绝缘层和导电插塞上，并且在其中具有暴露导电插塞的沟槽。 铜或铜合金导体基本上填充沟槽。

公开(公告)号：US06736701B1

公开(公告)日：2004-05-18

申请号：US09989838

申请日：2001-11-20

申请人： Shau-Lin Shue ,  Ying-Ho Chen ,  Wen-Chih Chiou ,  Tsu Shih ,  Syun-Ming Jang

发明人： Shau-Lin Shue ,  Ying-Ho Chen ,  Wen-Chih Chiou ,  Tsu Shih ,  Syun-Ming Jang

IPC分类号： B24B100

CPC分类号： B24B37/042 ,  B24B21/04

摘要： A new method is provided for the post-deposition treatment of copper lines. A damascene copper line pattern whereby a TaN barrier layer and a seed layer have been provided is polished. Under the first embodiment of the invention, the deposited copper is polished (Cu CMP), the surface of the wafer is rinsed using a first High Flow DI rinse that contains a TBA inhibitor. The TaN CMP is performed immediately following the first High Flow DI rinse. A second High Flow DI rinse is applied using DI water that contains TBA inhibitor. The required following rinse step is executed immediately after the second High Flow DI rinse has been completed. Under the second embodiment of the invention, the process of CMP has been divided in two distinct steps where the first step is aimed at corrosion elimination and the second step is aimed at elimination of mechanical damage to the polished copper. The processing conditions for the second processing step have been extended and optimized, thereby using a second belt of a CMP apparatus.

摘要翻译： 提供了一种新的铜线后处理方法。 抛光已经提供TaN阻挡层和种子层的镶嵌铜线图案。 在本发明的第一实施例中，抛光沉积的铜（Cu CMP），使用含有TBA抑制剂的第一高流量DI冲洗冲洗晶片的表面。 在第一次高流量DI冲洗之后立即执行TaN CMP。 使用含有TBA抑制剂的去离子水进行第二次高流量DI冲洗。 第二次高流量DI冲洗完成后立即执行所需的冲洗步骤。 在本发明的第二个实施方案中，CMP的方法分为两个不同的步骤，其中第一步骤旨在消除腐蚀，第二步骤旨在消除抛光铜的机械损伤。 第二处理步骤的处理条件已被扩展和优化，从而使用CMP设备的第二带。

公开(公告)号：US06635211B2

公开(公告)日：2003-10-21

申请号：US09888789

申请日：2001-06-25

申请人： Wen-Chih Chiou ,  Ying-Ho Chen ,  Tsu Shih ,  Syun-Ming Jang

发明人： Wen-Chih Chiou ,  Ying-Ho Chen ,  Tsu Shih ,  Syun-Ming Jang

IPC分类号： B29C3912

CPC分类号： B29C39/025 ,  B24B37/042 ,  B29C70/64 ,  B29C2793/009 ,  B29K2105/126 ,  B29K2105/128 ,  B29K2105/16 ,  B29L2031/709 ,  B29L2031/736

摘要： A continuous loop polishing pad that is reinforced by a reinforcing filler and a method for fabricating the polishing pad are described. The reinforced polishing pad is constructed by a sub-layer and a top layer, wherein the sub-layer defines an inner diameter of the polishing pad and contains a reinforcing filler with an aspect ratio of at least 10 oriented substantially in a circumferential direction of the continuous loop polishing pad. The top layer is laminated to the sub-layer with a top surface defining an outer diameter of the polishing pad, while both the sub-layer and the top layer are formed of a polymeric material. The invention further describes a method for fabricating the reinforced polishing pad in a continuous loop.

公开(公告)号：US06589872B1

公开(公告)日：2003-07-08

申请号：US09304302

申请日：1999-05-03

申请人： Jih-Churng Twu ,  Ying-Ho Chen ,  Tsu Shih ,  Syun-Ming Jang

发明人： Jih-Churng Twu ,  Ying-Ho Chen ,  Tsu Shih ,  Syun-Ming Jang

IPC分类号： H01K2120

CPC分类号： B24B37/042 ,  B24B49/00 ,  B24B57/02

摘要： The invention teaches a new method of applying slurry during the process of chemical mechanical polishing of copper surfaces. By varying the rate of slurry deposition, starting out with a low rate of slurry flow that is increased as the polishing process proceeds, the invention obtains good planarity for copper surfaces while saving on the amount of slurry that is being used for the copper surface polishing process.

摘要翻译： 本发明教导了在铜表面的化学机械抛光过程中施加浆料的新方法。 通过改变浆料沉积速率，随着抛光工艺的进行，随着浆料流动速度的降低而开始，本发明对于铜表面获得了良好的平面性，同时节省了用于铜表面抛光的浆料量 处理。

公开(公告)号：US06429118B1

公开(公告)日：2002-08-06

申请号：US09664414

申请日：2000-09-18

申请人： Ying-Ho Chen ,  Syun-Ming Jang ,  Jih-Churng Twu ,  Tsu Shih

发明人： Ying-Ho Chen ,  Syun-Ming Jang ,  Jih-Churng Twu ,  Tsu Shih

IPC分类号： H01L213213

CPC分类号： H01L21/76802 ,  H01L21/2855 ,  H01L21/7684 ,  H01L21/76877

摘要： An improved and new process, used for the elimination of copper line damage in damacene processing, is disclosed. By depositing copper by physical vapor deposition (PVD), sputtering, preferably by an ion metal plasma (IMP) scheme or chemical vapor deposition (CVD), the deposited copper fills pinholes or intra-cracks (micro-cracks), caused by poor gap filling of purely electrochemical deposition of copper plating. By this process or method, chemical attack on copper lines, by chemicals in the subsequent chemical mechanical polish (CMP) back and post-cleaning steps, is prevented.

摘要翻译： 公开了一种改进和新的方法，用于消除碲化氢处理中的铜线损伤。 通过物理气相沉积（PVD），优选通过离子金属等离子体（IMP）方案或化学气相沉积（CVD）沉积铜，沉积的铜填充由差的间隙引起的针孔或裂纹（微裂纹） 填充电镀纯电化学沉积。 通过该方法或方法，可以防止化学品在后续的化学机械抛光（CMP）背面和后清洗步骤中对铜线进行化学侵蚀。

公开(公告)号：US06391780B1

公开(公告)日：2002-05-21

申请号：US09378949

申请日：1999-08-23

申请人： Tsu Shih ,  Ying-Ho Chen ,  Jih-Churng Twu

发明人： Tsu Shih ,  Ying-Ho Chen ,  Jih-Churng Twu

IPC分类号： H01L21302

CPC分类号： H01L21/3212

摘要： A process for manufacturing damascene wiring in integrated circuits is described. Trenches in the top most layer are first over-filled with a soft metal (such as copper) and then a relatively thin layer of a hard material such as tantalum, tantalum nitride, titanium, titanium nitride etc is deposited on the copper surface Under a first set of control conditions CMP is then applied for just long enough to selectively remove this hard material layer from peaks in the copper surface while leaving it intact in the valleys. The control conditions for CMP are then adjusted so that CMP can proceed with material at the peaks being removed at a significantly faster rate than in the valleys. Thus, when the point is reached that all copper outside the trenches has been removed, the trenches are found to be just filled with a flat layer that has no dishing.

摘要翻译： 描述了在集成电路中制造镶嵌线的工艺。 首先用软金属（例如铜）填充最顶层的沟槽，然后在铜表面上沉积相对薄的硬质材料如钽，氮化钽，钛，氮化钛等层 第一组控制条件CMP然后施加足够长的时间以从铜表面的峰中选择性地去除该硬质材料层，同时将其完整地留在谷中。 然后调整CMP的控制条件，使得CMP可以以比在谷中明显更快的速率除去峰值处的材料继续进行。 因此，当达到沟槽外部的所有铜已经被去除的地方时，发现沟槽刚好填充有没有凹陷的平坦层。

公开(公告)号：US06383930B1

公开(公告)日：2002-05-07

申请号：US09902896

申请日：2001-07-12

申请人： Ying-Ho Chen ,  Wen-Chih Chiou ,  Tsu Shih ,  Syun-Ming Jang

发明人： Ying-Ho Chen ,  Wen-Chih Chiou ,  Tsu Shih ,  Syun-Ming Jang

IPC分类号： H01K2144

CPC分类号： H01L21/76885 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new method is provided that affects the polishing rate of the surface of a layer of copper, that has been deposited over the surface of a layer of dielectric. Copper damascene structures have been created in the surface of the layer of dielectric, the layer of dielectric also overlies an alignment mark. The surface of the layer of dielectric that is aligned with the alignment mark is provided with dummy damascene structures, assuring equal polishing rates for active damascene structures and the surface region of the layer of dielectric overlying an alignment mark.

摘要翻译： 提供了一种新的方法，其影响已经沉积在电介质层的表面上的铜层的表面的抛光速率。 在电介质层的表面已经形成铜镶嵌结构，电介质层也覆盖对准标记。 与对准标记对准的电介质层的表面设置有虚拟镶嵌结构，确保活性镶嵌结构的相同抛光速率和覆盖对准标记的电介质层的表面区域。