公开(公告)号：US20240339397A1

公开(公告)日：2024-10-10

申请号：US18746055

申请日：2024-06-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Min-Shiang Hsu ,  Yu-Han Tsai ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/76877

Abstract: An interconnection structure includes a first interconnection level, a second interconnection level, a third interconnection level, and a super via structure. The second interconnection level is disposed on the first interconnection level, and the third interconnection level is disposed on the second interconnection level. The second interconnection level includes a second conductive layer and a block layer disposed in a dielectric layer. A bottom surface of the block layer is lower than a top surface of the second conductive layer in a vertical direction. The block layer is disposed between a first conductive layer of the first interconnection level and a third conductive layer of the third interconnection level in the vertical direction. The super via structure penetrates through the block layer and the second interconnection level in the vertical direction and electrically connects the first conductive layer and the third conductive layer.

公开(公告)号：US12007435B2

公开(公告)日：2024-06-11

申请号：US17114515

申请日：2020-12-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chih Chang ,  Yi-Hsiu Chen ,  Yuan-Fu Ko ,  Chih-Sheng Chang

IPC: G01R31/28

CPC classification number: G01R31/2884 ,  G01R31/2894 ,  Y10T29/49004

Abstract: A method of copper hillock detecting includes the following steps. A testkey structure is disposed on a substrate, wherein the testkey structure includes a lower metallization layer, an upper metallization layer, and a dielectric layer between the lower metallization layer and the upper metallization layer. A force voltage difference is applied to the lower metallization layer and the upper metallization layer under a test temperature and stress time. A changed sensing voltage difference to the lower metallization layer and the upper metallization layer is detected for detecting copper hillock.

公开(公告)号：US20220392798A1

公开(公告)日：2022-12-08

申请号：US17888502

申请日：2022-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chih Chang ,  Yuan-Fu Ko ,  Chih-Sheng Chang

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/02 ,  H01L23/532

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.

公开(公告)号：US11515159B2

公开(公告)日：2022-11-29

申请号：US17137320

申请日：2020-12-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chih Chang ,  Yuan-Fu Ko ,  Chih-Sheng Chang

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/02 ,  H01L21/47 ,  H01L21/311

Abstract: The present invention further provides a method for forming a semiconductor device, the method including: first, a target layer is provided, an etching stop layer is formed on the target layer, a top oxide layer is formed on the etching stop layer, afterwards, a first photoresist layer is formed on the top oxide layer, and a first etching process is then performed, to form a plurality of first trenches in the top oxide layer. Next, a second photoresist layer is formed on the top oxide layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the top oxide layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the etching stop layer and parts of the target layer.

公开(公告)号：US20220178992A1

公开(公告)日：2022-06-09

申请号：US17114515

申请日：2020-12-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chih Chang ,  Yi-Hsiu Chen ,  Yuan-Fu Ko ,  Chih-Sheng Chang

IPC: G01R31/28

Abstract: A method of copper hillock detecting includes the following steps. A testkey structure is disposed on a substrate, wherein the testkey structure includes a lower metallization layer, an upper metallization layer, and a dielectric layer between the lower metallization layer and the upper metallization layer. A force voltage difference is applied to the lower metallization layer and the upper metallization layer under a test temperature and stress time. A changed sensing voltage difference to the lower metallization layer and the upper metallization layer is detected for detecting copper hillock.

公开(公告)号：US20210151321A1

公开(公告)日：2021-05-20

申请号：US17137320

申请日：2020-12-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chih Chang ,  Yuan-Fu Ko ,  Chih-Sheng Chang

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/02 ,  H01L21/47 ,  H01L21/311

Abstract: The present invention further provides a method for forming a semiconductor device, the method including: first, a target layer is provided, an etching stop layer is formed on the target layer, a top oxide layer is formed on the etching stop layer, afterwards, a first photoresist layer is formed on the top oxide layer, and a first etching process is then performed, to form a plurality of first trenches in the top oxide layer. Next, a second photoresist layer is formed on the top oxide layer, portion of the second photoresist layer fills in each first trench, a second etching process is then performed to form a plurality of second trenches in the top oxide layer, and using the remaining etching stop layer as a hard mask, a third etching process is performed to remove parts of the etching stop layer and parts of the target layer.

公开(公告)号：US20210082839A1

公开(公告)日：2021-03-18

申请号：US17103584

申请日：2020-11-24

Applicant: United Microelectronics Corp.

Inventor： Shih-Che Huang ,  Shih-Hsien Chen ,  Ching-Li Yang ,  Chih-Sheng Chang

IPC: H01L23/58 ,  H01L23/10 ,  H01L23/522 ,  H01L21/48 ,  H01L23/00 ,  H01L21/768

Abstract: A method of manufacturing a die seal ring including the following steps is provided. A dielectric layer is formed on a substrate. Conductive layers stacked on the substrate are formed in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is formed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is formed between a sidewall of the second conductive portion and the dielectric layer.

公开(公告)号：US20190081000A1

公开(公告)日：2019-03-14

申请号：US15730744

申请日：2017-10-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Yi Weng ,  Shih-Che Huang ,  Ching-Li Yang ,  Chih-Sheng Chang

IPC: H01L23/532 ,  H01L23/522

Abstract: A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.

公开(公告)号：US20180061752A1

公开(公告)日：2018-03-01

申请号：US15271221

申请日：2016-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Che Huang ,  Ching-Li Yang ,  Yu-Cheng Tung ,  Yu-Tsung Lai ,  Chih-Sheng Chang

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/53295 ,  H01L28/60

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a capacitor is formed on the substrate and a hard mask on the capacitor, in which the capacitor includes a bottom electrode, a capacitor dielectric layer, and a top electrode. Next, a protective layer is formed on the sidewalls of the top electrode and the bottom electrode, in which the protective layer includes metal oxide.

公开(公告)号：US09773860B1

公开(公告)日：2017-09-26

申请号：US15257930

申请日：2016-09-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Tsung Lai ,  Ching-Li Yang ,  Yu-Cheng Tung ,  Shih-Che Huang ,  Chih-Sheng Chang

IPC: H01L49/02

CPC classification number: H01L28/60

Abstract: A method for fabricating a capacitor is disclosed. First, a substrate is provided, a bottom electrode and a capacitor dielectric layer are formed on the substrate, a conductive layer is formed on the capacitor dielectric layer, a patterned hard mask is formed on the conductive layer, a patterned hard mask is used to remove part of the conductive layer to form a top electrode, the patterned hard mask is removed, and a protective layer is formed on a top surface and sidewalls of top electrode. Preferably, the protective layer includes metal oxides.