公开(公告)号：US20220013713A1

公开(公告)日：2022-01-13

申请号：US16988707

申请日：2020-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Jung Chiu ,  Ya-Sheng Feng ,  I-Ming Tseng ,  Yi-An Shih ,  Yu-Chun Chen ,  Yi-Hui Lee ,  Chung-Liang Chu ,  Hsiu-Hao Hu

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

公开(公告)号：US10971676B2

公开(公告)日：2021-04-06

申请号：US16731064

申请日：2019-12-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Jian-Cheng Chen ,  Yu-Ping Wang ,  Yu-Ruei Chen

IPC: H01L27/22 ,  H01L43/02 ,  G11C11/16 ,  H01L27/02

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, wherein the ring of MTJ region comprises a first MTJ, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, each of the metal interconnect patterns includes a first metal interconnection connected to the first MTJ directly.

公开(公告)号：US20210098342A1

公开(公告)日：2021-04-01

申请号：US17121696

申请日：2020-12-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Yu-Ruei Chen

IPC: H01L23/48 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a second gate structure, a first slot contact structure, a first gate contact structure, and a second gate contact structure. The substrate includes a first active region and a second active region elongated in a first direction respectively. The first gate structure, the second gate structure, and the first slot contact structure are continuously elongated in a second direction respectively. The first gate contact structure and the second gate contact structure are disposed at two opposite sides of the first slot contact structure in the first direction respectively.

公开(公告)号：US10903143B1

公开(公告)日：2021-01-26

申请号：US16572627

申请日：2019-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Yu-Ruei Chen

IPC: H01L21/8234 ,  H01L23/48 ,  H01L29/78 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate, an isolation structure, a first gate structure, a second gate structure, a first slot contact structure, a first gate contact structure, and a second gate contact structure. The substrate includes a first active region and a second active region elongated in a first direction respectively. The first gate structure, the second gate structure, and the first slot contact structure are elongated in a second direction respectively. The first gate contact structure and the second gate contact structure are disposed at two opposite sides of the first slot contact structure in the first direction respectively and disposed between the first active region and the second active region in the second direction. A length of the first gate contact structure and a length of the second gate contact structure in the second direction are less than a length of the isolation structure in the second direction.

公开(公告)号：US10854592B2

公开(公告)日：2020-12-01

申请号：US16175867

申请日：2018-10-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Yu-Ruei Chen ,  Yu-Hsiang Lin

IPC: H01L27/02 ,  H01L27/088 ,  H01L21/8234 ,  H03K19/173

Abstract: A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region, and flexible extended dummy cells arranged in rows and columns filling up remaining dummy region. The unit dummy cell includes exactly one base dummy cell and exactly two fixed dummy cells at opposite sides of the base dummy cell in row direction or in column direction and the flexible extended dummy cell includes at least two base dummy units and a plurality of flexible dummy units at two opposite sides of the two base dummy units in row direction or in column direction. The base dummy cell consists of at least one fin, at least one gate and at least one contact, while the flexible dummy cell consists of one gate and one contact without any fin.

公开(公告)号：US20200212030A1

公开(公告)日：2020-07-02

申请号：US16255786

申请日：2019-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Chih-Hsien Tang ,  Yu-Ruei Chen ,  Ya-Huei Tsai ,  Rai-Min Huang ,  Chueh-Fei Tai

IPC: H01L27/02 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  G03F1/36

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.

公开(公告)号：US10153265B1

公开(公告)日：2018-12-11

申请号：US15681439

申请日：2017-08-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Yu-Ruei Chen ,  Yu-Hsiang Lin

IPC: H01L27/02 ,  H01L27/088 ,  H01L21/8234

Abstract: A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region, and flexible extended dummy cells arranged in rows and columns filling up remaining dummy region. The unit dummy cell includes exactly one base dummy cell and exactly two fixed dummy cells at opposite sides of the base dummy cell in row direction or in column direction and the flexible extended dummy cell includes at least two base dummy units and a plurality of flexible dummy units at two opposite sides of the two base dummy units in row direction or in column direction. The base dummy cell consists of at least one fin, at least one gate and at least one contact, while the flexible dummy cell consists of one gate and one contact without any fin.

公开(公告)号：US20170365675A1

公开(公告)日：2017-12-21

申请号：US15183800

申请日：2016-06-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Ying-Chiao Wang ,  Hon-Huei Liu ,  Jyh-Shyang Jenq ,  Chung-Liang Chu ,  Yu-Ruei Chen

IPC: H01L29/423 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/02

CPC classification number: H01L21/32139 ,  H01L27/0207

Abstract: A dummy pattern arrangement and a method of arranging dummy patterns are provided in the present invention. The dummy pattern arrangement includes a substrate with a dummy region, a plurality of first base dummy cells arranged spaced apart from each other along a first direction in the dummy region, and two first edge dummy cells arranged respectively at two opposite sides of the first base dummy cells along the first direction in the dummy region.