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公开(公告)号：US10707214B2
公开(公告)日：2020-07-07
申请号：US15990837
申请日：2018-05-29
Inventor： Chia-Chen Wu , Yi-Wei Chen , Chi-Mao Hsu , Kai-Jiun Chang , Chih-Chieh Tsai , Pin-Hong Chen , Tsun-Min Cheng , Yi-An Huang
IPC: H01L27/108 , C23C14/06 , C23C14/34 , C23C14/58 , H01L21/285
Abstract: A method of fabricating a cobalt silicide layer includes providing a substrate disposed in a chamber. A deposition process is performed to form a cobalt layer covering the substrate. The deposition process is performed when the temperature of the substrate is between 50° C. and 100° C., and the temperature of the chamber is between 300° C. and 350° C. After the deposition process, an annealing process is performed to transform the cobalt layer into a cobalt silicide layer. The annealing process is performed when the substrate is between 300° C. and 350° C., and the duration of the annealing process is between 50 seconds and 60 seconds.
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Patent Agency Ranking
公开(公告)号：US20190318933A1
公开(公告)日：2019-10-17
申请号：US15986797
申请日：2018-05-22
Inventor： Tzu-Hao Liu , Yi-Wei Chen , Tsun-Min Cheng , Kai-Jiun Chang , Chia-Chen Wu , Yi-An Huang , Po-Chih Wu , Pin-Hong Chen , Chun-Chieh Chiu , Tzu-Chieh Chen , Chih-Chien Liu , Chih-Chieh Tsai , Ji-Min Lin
IPC: H01L21/28 , H01L27/108 , G11C11/4097
Abstract: A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.
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公开(公告)号：US10290638B1
公开(公告)日：2019-05-14
申请号：US15964089
申请日：2018-04-27
Inventor： Yi-Wei Chen , Tsun-Min Cheng , Shih-Fang Tzou , Chih-Chieh Tsai , Kai-Jiun Chang
IPC: H01L27/108 , H01L23/532 , H01L21/285 , H01L21/768 , H01L23/528 , H01L21/02 , H01L21/3105 , H01L21/265 , H01L29/10 , H01L21/306
Abstract: A method of forming dynamic random access memory (DRAM) device, comprises the following steps. First of all, a plurality of active areas is formed in a substrate along a first direction. Next, a plurality of buried gates disposed in the substrate is formed along a second trench extending along a second direction across the first direction. Then, a plurality of bit lines is formed over the buried gates and extended along a third direction across the first direction and the second direction, wherein each of the bit lines comprises a polysilicon layer, a barrier layer and a metal layer and the barrier layer is formed through a radio frequency physical vapor deposition (RF-PVD) process.
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公开(公告)号：US20190013320A1
公开(公告)日：2019-01-10
申请号：US15986780
申请日：2018-05-22
Inventor： Tzu-Chieh Chen , Pin-Hong Chen , Chih-Chieh Tsai , Chia-Chen Wu , Yi-An Huang , Kai-Jiun Chang , Tsun-Min Cheng , Yi-Wei Chen
IPC: H01L27/108 , H01L23/31
Abstract: A semiconductor memory device is provided, and which includes a substrate, plural gates, plural plugs, a capacitor structure and a conducting cap layer. The gates are disposed within the substrate, and the plugs are disposed on the substrate, with each plug electrically connected to two sides of each gate on the substrate. The capacitor structure is disposed on the substrate, and the capacitor structure includes plural capacitors, with each capacitor electrically connected to the plugs respectively. The conducting cap layer covers the top surface and sidewalls of the capacitor structure. Also, the semiconductor memory device further includes an adhesion layer and an insulating layer. The adhesion layer covers the conducting cap layer and the capacitor structure, and the insulating layer covers the adhesion layer.
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35.发明申请公开(公告)号：US20180190662A1
公开(公告)日：2018-07-05
申请号：US15854825
申请日：2017-12-27
Inventor： Tzu-Chin Wu , Wei-Hsin Liu , Yi-Wei Chen , Mei-Ling Chen , Chia-Lung Chang , Ching-Hsiang Chang , Jui-Min Lee , Tsun-Min Cheng , Lin-Chen Lu , Shih-Fang Tzou , Kai-Jiun Chang , Chih-Chieh Tsai , Tzu-Chieh Chen , Chia-Chen Wu
IPC: H01L27/108 , H01L21/033 , H01L23/532 , H01L23/528 , H01L21/768 , H01L21/285
CPC classification number: H01L27/10885 , H01L21/0332 , H01L21/0337 , H01L21/28568 , H01L21/32139 , H01L21/76846 , H01L21/76877 , H01L23/528 , H01L23/53266 , H01L23/53271 , H01L27/10823 , H01L27/10876
Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following. A hard mask layer is formed on a metal stack by a chemical vapor deposition process importing nitrogen (N2) gases and then importing amonia (NH3) gases. The present invention also provides a bit line gate structure of a dynamic random access memory (DRAM) including a metal stack and a hard mask. The metal stack includes a polysilicon layer, a titanium layer, a titanium nitride layer, a first tungsten nitride layer, a tungsten layer and a second tungsten nitride layer stacked from bottom to top. The hard mask is disposed on the metal stack.
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公开(公告)号：US09859123B1
公开(公告)日：2018-01-02
申请号：US15472308
申请日：2017-03-29
Inventor： Chia-Chen Wu , Pin-Hong Chen , Kai-Jiun Chang , Yi-An Huang , Chih-Chieh Tsai , Tzu-Chieh Chen , Tsun-Min Cheng , Yi-Wei Chen
IPC: H01L21/28 , H01L21/285 , H01L21/768 , H01L21/321 , H01L29/66
CPC classification number: H01L21/28518 , H01L21/321 , H01L21/76889 , H01L29/665
Abstract: A method for fabricating a semiconductor device is disclosed. A substrate having a conductive region is provided. A metal layer is deposited on the conductive region. The metal layer reacts with the conductive region to form a first metal silicide layer. A TiN layer is deposited on the metal layer. A SiN layer is deposited on the TiN layer. An annealing process is performed to convert the first metal silicide layer into a second metal silicide layer.
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