公开(公告)号：US20210335669A1

公开(公告)日：2021-10-28

申请号：US17367150

申请日：2021-07-02

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/02 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8249 ,  H01L29/423

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping the gate region.

公开(公告)号：US10796964B2

公开(公告)日：2020-10-06

申请号：US16428651

申请日：2019-05-31

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

IPC: H01L29/06 ,  H01L27/02 ,  H01L21/8249 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.

公开(公告)号：US20200212201A1

公开(公告)日：2020-07-02

申请号：US16813768

申请日：2020-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu ,  Ching-Chung Yang ,  Ping-Hung Chiang

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

Abstract: A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.

公开(公告)号：US20190287860A1

公开(公告)日：2019-09-19

申请号：US16428651

申请日：2019-05-31

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/8249 ,  H01L29/49 ,  H01L27/02 ,  H01L29/06 ,  H01L29/423

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.

公开(公告)号：US20190006528A1

公开(公告)日：2019-01-03

申请号：US15660982

申请日：2017-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kai-Kuen Chang ,  Ching-Chung Yang

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/40

Abstract: A high voltage device includes a semiconductor substrate, an ion well, a Schottky diode in the ion well, an isolation structure in the ion well surrounding the Schottky diode, and an assistant gate surrounding the Schottky diode. The assistant gate is disposed only on the isolation structure and is not in direct contact with the ion well.

公开(公告)号：US20170330947A1

公开(公告)日：2017-11-16

申请号：US15667633

申请日：2017-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Wen-Fang Lee ,  Nien-Chung Li ,  Chih-Chung Wang

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L23/535 ,  G06F17/50

CPC classification number: H01L29/4238 ,  G06F17/5072 ,  H01L23/535 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7836 ,  H01L29/785

Abstract: A metal-oxide semiconductor transistor includes a substrate, a gate insulating layer disposed on a surface of the substrate, and a metal gate disposed on the gate insulating layer, wherein at least one of the length or the width of the metal gate is greater than or equal to approximately 320 nanometers, and the metal gate has at least one plug hole. The metal-oxide semiconductor transistor further includes at least one insulating plug disposed in the plug hole and two diffusion regions disposed respectively at two sides of the metal gate in the substrate.

公开(公告)号：US20170243950A1

公开(公告)日：2017-08-24

申请号：US15047644

申请日：2016-02-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Liang Liu ,  Shih-Yin Hsiao ,  Ching-Chung Yang

IPC: H01L29/66 ,  H01L21/223

CPC classification number: H01L29/66598 ,  H01L21/26513 ,  H01L29/7833

Abstract: A method of fabricating a transistor with reduced hot carrier injection effects includes providing a substrate covered by a gate material layer. Later, the gate material layer is patterned into a gate electrode. Then, a mask layer is formed to cover part of the gate electrode and expose two ends of the gate electrode. Finally, a first implantation process is performed to implant dopants through the exposed two ends of the gate electrode into the substrate directly under the gate electrode to form two LDD regions by taking the mask layer as a mask.

公开(公告)号：US09029932B2

公开(公告)日：2015-05-12

申请号：US14010611

申请日：2013-08-27

Applicant: United Microelectronics Corp.

Inventor： Ze-Wei Jhou ,  Ching-Chung Yang

IPC: H01L29/788 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7889 ,  H01L27/11519 ,  H01L27/11558 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7831 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7885

Abstract: A programmable device and a method of manufacturing the same are provided. A programmable device comprises a substrate having a source region, a drain region and a diffusion region adjacent to the source region and the drain region; a channel coupling the source region and the drain region; a floating gate formed of a conductive material and positioned on the substrate and corresponding to the channel; and a trench formed in the diffusion region at the substrate, wherein the floating gate extends to the trench, and the conductive material covers a sidewall of the trench.

Abstract translation: 提供了一种可编程装置及其制造方法。 可编程器件包括具有源极区，漏极区和邻近源极区和漏极区的扩散区的衬底; 耦合源极区和漏极区的沟道; 由导电材料形成并位于衬底上并对应于沟道的浮动栅; 以及形成在所述基板的所述扩散区域中的沟槽，其中所述浮栅延伸到所述沟槽，并且所述导电材料覆盖所述沟槽的侧壁。

公开(公告)号：US12087635B2

公开(公告)日：2024-09-10

申请号：US18335154

申请日：2023-06-15

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/8249 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/823425 ,  H01L21/823437 ,  H01L21/8249 ,  H01L27/0251 ,  H01L29/0607 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4925 ,  H01L29/7832 ,  H01L29/7835 ,  H01L29/78

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping the gate region.

公开(公告)号：US20230411495A1

公开(公告)日：2023-12-21

申请号：US17867640

申请日：2022-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chung Yang

IPC: H01L29/66 ,  H01L21/266 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/266 ,  H01L21/26513 ,  H01L29/7833 ,  H01L29/66492

Abstract: A semiconductor device includes a substrate of first conductivity type; a first heavily doped region and a second heavily doped region of second conductivity type spaced apart from the first heavily doped region, located in the substrate; a channel region in the substrate and between the first heavily doped region and the second heavily doped region; a gate disposed on the channel region; a hard mask layer covering a top surface and a sidewall of the gate; and a spacer disposed on a sidewall of the hard mask layer.