公开(公告)号：US10147800B2

公开(公告)日：2018-12-04

申请号：US15047644

申请日：2016-02-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Liang Liu ,  Shih-Yin Hsiao ,  Ching-Chung Yang

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/78

Abstract: A method of fabricating a transistor with reduced hot carrier injection effects includes providing a substrate covered by a gate material layer. Later, the gate material layer is patterned into a gate electrode. Then, a mask layer is formed to cover part of the gate electrode and expose two ends of the gate electrode. Finally, a first implantation process is performed to implant dopants through the exposed two ends of the gate electrode into the substrate directly under the gate electrode to form two LDD regions by taking the mask layer as a mask.

公开(公告)号：US10020393B2

公开(公告)日：2018-07-10

申请号：US14886108

申请日：2015-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Chia-Min Hung

IPC: H01L29/78 ,  H01L29/24 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/4763 ,  H01L21/471 ,  H01L21/4757 ,  H01L21/441

CPC classification number: H01L29/7823 ,  H01L21/441 ,  H01L21/471 ,  H01L21/47573 ,  H01L21/4763 ,  H01L21/47635 ,  H01L29/0611 ,  H01L29/0653 ,  H01L29/24 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41725 ,  H01L29/66689 ,  H01L29/66969 ,  H01L29/7816

Abstract: The present invention provides a laterally diffused metal-oxide-semiconductor (LDMOS) transistor and a manufacturing method thereof. The LDMOS transistor includes a semiconductor substrate, an insulation structure, agate structure, and a plurality of floating electrodes. The insulation structure is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The floating electrodes are embedded in the insulation structure, wherein the floating electrode closest to the gate structure protrudes from a top surface of the insulation structure or the gate structure includes at least one branch portion embedded in the insulation structure, and the floating electrodes are separated from the gate structure.

公开(公告)号：US20180114842A1

公开(公告)日：2018-04-26

申请号：US15352558

申请日：2016-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu ,  Ching-Chung Yang ,  Ping-Hung Chiang

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/66545 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66621 ,  H01L29/7834

Abstract: A high voltage semiconductor device and a manufacturing method thereof are provided in the present invention. A recess is formed in a semiconductor substrate, and a gate dielectric layer and a main gate structure are formed in the recess. Therefore, the high voltage semiconductor device formed by the manufacturing method of the present invention may include the main gate structure lower than a top surface of an isolation structure formed in the semiconductor substrate. Problems about integrated manufacturing processes of the high voltage semiconductor device and other kinds of semiconductor devices when the gate structure is relatively high because of the thicker gate dielectric layer required in the high voltage semiconductor device may be improved accordingly.

公开(公告)号：US20180108528A1

公开(公告)日：2018-04-19

申请号：US15292775

申请日：2016-10-13

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Shu-Wen Lin ,  Ke-Feng Lin ,  Hsin-Liang Liu ,  Chang-Lin Chen

IPC: H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L21/28141 ,  H01L21/28123 ,  H01L21/28211 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/78

Abstract: A method for forming a gate oxide layer on a substrate is provided, in which a region of the substrate is defined out by a shallow trench isolation (STI) structure. An oxide layer covers over the substrate and a mask layer with an opening to expose oxide layer corresponding to the region with an interface edge of the STI structure. The method includes forming a silicon spacer on a sidewall of the opening. A cleaning process is performed through the opening to expose the substrate at the region. An oxidation process is performed on the substrate at the region to form the gate oxide layer, wherein the silicon spacer is also oxidized to merge to an edge of the gate oxide layer.

公开(公告)号：US20180097104A1

公开(公告)日：2018-04-05

申请号：US15820467

申请日：2017-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kuan-Liang Liu ,  Ching-Chung Yang ,  Kai-Kuen Chang ,  Ping-Hung Chiang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7823 ,  H01L21/033 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66681

Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.

公开(公告)号：US09812327B2

公开(公告)日：2017-11-07

申请号：US14863177

申请日：2015-09-23

Applicant: United Microelectronics Corp.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L21/28 ,  H01L29/423 ,  H01L27/11536 ,  H01L27/11539

CPC classification number: H01L21/28273 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42336

Abstract: Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. A method of forming a memory device is further provided.

公开(公告)号：US09755046B2

公开(公告)日：2017-09-05

申请号：US15406355

申请日：2017-01-13

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang

IPC: H01L21/02 ,  H01L29/76 ,  H01L31/062 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/311

CPC classification number: H01L29/66492 ,  H01L21/2652 ,  H01L21/31111 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7833

Abstract: A method of forming a semiconductor device is provided. At least two shallow trenches are formed in a substrate. An insulating layer is formed on surfaces of the substrate and the shallow trenches. A conductive layer is formed on the substrate between the shallow trenches. At least one spacer is formed on a sidewall of the conductive layer, wherein the spacer fills up each shallow trench.

公开(公告)号：US20170110589A1

公开(公告)日：2017-04-20

申请号：US14882663

申请日：2015-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chung Yang ,  Shih-Yin Hsiao

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/4238 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/78

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a diffusion region, a first oxide layer, a second oxide layer and a polysilicon layer. The diffusion region is formed in the substrate and has a source and a drain extended along a first direction. The first oxide layer is formed on the substrate. The second oxide layer is formed in the substrate and adjacent to the drain. The polysilicon layer is formed on the substrate and has a first region, a second region, and a third region. The second region is formed on an edge of the second oxide layer and between the first region and the third region. A width of the second region is less than a width of the first region and a width of the third region along the first direction.

公开(公告)号：US20170077250A1

公开(公告)日：2017-03-16

申请号：US14922209

申请日：2015-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kai-Kuen Chang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4232 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor transistor device and a manufacturing method thereof. First, a semiconductor substrate is provided and a dielectric layer and a conductive layer sequentially stacked on the semiconductor substrate. Then, the conductive layer is patterned to form a gate and a dummy gate disposed at a first side of the gate and followed by forming a first spacer between the gate and the dummy gate and a second spacer at a second side of the gate opposite to the first side, wherein the first spacer includes an indentation. Subsequently, the dummy gate is removed.

Abstract translation: 本发明提供一种高压金属氧化物半导体晶体管器件及其制造方法。 首先，提供半导体衬底，并且依次层叠在半导体衬底上的电介质层和导电层。 然后，对导电层进行构图以形成设置在栅极第一侧的栅极和伪栅极，然后在栅极和伪栅极之间形成第一间隔物，并在门的第二侧形成第二间隔物， 第一侧，其中第一间隔件包括凹陷。 随后，去除虚拟门。

公开(公告)号：US09577069B1

公开(公告)日：2017-02-21

申请号：US15136982

申请日：2016-04-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chieh Pu ,  Ping-Hung Chiang ,  Chang-Po Hsiung ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang ,  Kuan-Lin Liu

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/308 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L21/02238 ,  H01L21/28123 ,  H01L21/3081 ,  H01L29/0649 ,  H01L29/66575 ,  H01L29/66681

Abstract: A method of fabricating a MOS device is disclosed. A substrate having an active area (AA) silicon portion and shallow trench isolation (STI) region surrounding the active area is provided. A hard mask is formed on the substrate. A portion of the hard mask is removed to form an opening on the AA silicon portion. The opening exposes an edge of the STI region. The AA silicon portion is recessed through the opening to a predetermined depth to form a silicon spacer along a sidewall of the STI region in a self-aligned manner. An oxidation process is performed to oxidize the AA silicon portion and the silicon spacer to form a gate oxide layer.

Abstract translation: 公开了制造MOS器件的方法。 提供了具有有源区（AA）硅部分和围绕有源区的浅沟槽隔离（STI）区的衬底。 在基板上形成硬掩模。 去除硬掩模的一部分以在AA硅部分上形成开口。 开口露出STI区域的边缘。 AA硅部分通过开口凹入预定深度，以自对准的方式沿着STI区域的侧壁形成硅间隔物。 进行氧化处理以氧化AA硅部分和硅间隔物以形成栅极氧化物层。