公开(公告)号：US09324610B2

公开(公告)日：2016-04-26

申请号：US14455939

申请日：2014-08-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jia-Rong Wu ,  Tsung-Hung Chang ,  Ching-Ling Lin ,  Yi-Hui Lee ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chun-Hsien Lin

IPC: H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L23/485 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/665 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有至少一个金属栅极的衬底，与所述至少一个金属栅极的两侧相邻的源极/漏极区域以及围绕所述至少一个金属栅极的层间电介质层 ; 在所述ILD层中形成多个接触孔以暴露所述源/漏区; 在所述接触孔中形成第一金属层; 执行第一热处理过程; 并执行第二热处理过程。

公开(公告)号：US20160020104A1

公开(公告)日：2016-01-21

申请号：US14334680

申请日：2014-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Lin ,  An-Chi Liu ,  Hsiao-Pang Chou

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/306

CPC classification number: H01L21/28088 ,  H01L21/3212 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7843

Abstract: A metal gate process for polishing and oxidizing includes the following steps. A first dielectric layer having a trench is formed on a substrate. A barrier layer and a metal layer are formed sequentially to cover the trench and the first dielectric layer. A first chemical mechanical polishing process including a slurry of H2O2 with the concentration of 0˜0.5 weight percent (wt. %) is performed to polish the metal layer until the barrier layer on the first dielectric layer is exposed. A second chemical mechanical polishing process including a slurry of H2O2 with the concentration higher than 1 weight percent (wt. %) is performed to polish the barrier layer as well as oxidize a surface of the metal layer remaining in the trench until the first dielectric layer is exposed, thereby a metal oxide layer being formed on the metal layer.

Abstract translation: 用于抛光和氧化的金属浇口工艺包括以下步骤。 在衬底上形成具有沟槽的第一电介质层。 依次形成阻挡层和金属层以覆盖沟槽和第一介电层。 执行包括浓度为0〜0.5重量％（重量％）的H 2 O 2的浆料的第一化学机械抛光工艺，以抛光金属层直到暴露第一​​介电层上的阻挡层。 执行包括浓度高于1重量％（重量％）的H 2 O 2的浆料的第二化学机械抛光方法以抛光阻挡层以及氧化残留在沟槽中的金属层的表面，直到第一介电层 被暴露，从而在金属层上形成金属氧化物层。

公开(公告)号：US20150076623A1

公开(公告)日：2015-03-19

申请号：US14025833

申请日：2013-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region.

Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 该方法包括以下步骤：提供具有NMOS区和PMOS区的衬底; 在NMOS区域和PMOS区域分别形成虚拟栅极; 从所述NMOS区域和所述PMOS区域中的每一个去除所述伪栅极; 在NMOS区域和PMOS区域上形成n型功函数层; 去除PMOS区域中的n型功函数层; 在NMOS区域和PMOS区域上形成p型功函数层; 以及在NMOS区域和PMOS区域的p型功函数层上沉积低电阻金属层。

公开(公告)号：US20250081510A1

公开(公告)日：2025-03-06

申请号：US18950223

申请日：2024-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shou-Wan Huang ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first fin-shaped structure extending along a first direction on the first region, a double diffusion break (DDB) structure extending along a second direction to divide the first fin-shaped structure into a first portion and a second portion, and a first gate structure and a second gate structure extending along the second direction on the DDB structure.

公开(公告)号：US12119272B2

公开(公告)日：2024-10-15

申请号：US18233331

申请日：2023-08-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Chi-Mao Hsu ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Chun-Hsien Lin

IPC: H01L21/00 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823821 ,  H01L27/0924

Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a single diffusion break (SDB) structure in the fin-shaped structure to divide the first fin-shaped structure into a first portion and a second portion, and more than two gate structures on the SDB structure. Preferably, the more than two gate structures include a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure disposed on the SDB structure.

公开(公告)号：US12114508B2

公开(公告)日：2024-10-08

申请号：US17548607

申请日：2021-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Chun-Hsien Lin

IPC: H10B53/30

CPC classification number: H10B53/30

Abstract: A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

公开(公告)号：US12041784B2

公开(公告)日：2024-07-16

申请号：US17491509

申请日：2021-09-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Hon-Huei Liu ,  Chun-Hsien Lin

IPC: H10B53/30 ,  H01L27/12 ,  H01L27/13 ,  H10B51/00

CPC classification number: H10B53/30 ,  H01L27/1207 ,  H01L27/13

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal-oxide semiconductor (MOS) transistor on a substrate, forming an interlayer dielectric (ILD) layer on the MOS transistor, forming a ferroelectric field effect transistor (FeFET) on the ILD layer, and forming a ferroelectric random access memory (FeRAM) on the ILD layer. The formation of the FeFET further includes first forming a semiconductor layer on the ILD layer, forming a gate structure on the semiconductor layer, and then forming a source/drain region adjacent to the gate structure.

公开(公告)号：US20240213247A1

公开(公告)日：2024-06-27

申请号：US18107983

申请日：2023-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Lin ,  Zen-Jay Tsai ,  Chun-Hsien Lin

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/0924

Abstract: A method for fabricating a semiconductor device includes providing a substrate having a first region and a second region, forming a first gate dielectric layer on the first region, forming a second gate dielectric layer on the second region, and forming a first gate structure on the first gate dielectric layer and the second gate dielectric layer. Preferably, the first gate dielectric layer and the second gate dielectric layer have different thicknesses.

公开(公告)号：US11862622B2

公开(公告)日：2024-01-02

申请号：US17348784

申请日：2021-06-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Yuan Wu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chen-Hsien Hsu ,  Chien-Hung Chen ,  Chun-Hsien Lin

IPC: H01L27/02 ,  H03K19/20

CPC classification number: H01L27/0207 ,  H03K19/20

Abstract: An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.

公开(公告)号：US11778917B2

公开(公告)日：2023-10-03

申请号：US16985206

申请日：2020-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Wei Liu ,  Jia-Feng Fang ,  Chun-Hsien Lin

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) stack on a substrate, performing an etching process to remove the MTJ stack for forming a MTJ, performing a deposition process to form a polymer on a sidewall of the MTJ, and removing the polymer to form a rough surface on the sidewall of the MTJ. Preferably, the MTJ could include a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer, in which the rough surface could appear on sidewall of the pinned layer, sidewall of the barrier layer, and/or sidewall of the free layer.