公开(公告)号：US20180108656A1

公开(公告)日：2018-04-19

申请号：US15347797

申请日：2016-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Tong-Jyun Huang ,  Shih-Hung Tsai ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/308 ,  H01L21/306 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851

Abstract: An asymmetrical fin structure includes a substrate. The substrate includes a top surface. A fin element extends from the substrate and connects to the substrate. The fin element includes two sidewalls respectively disposed at two opposite sides of the fin element. The sidewalls contact the top surface of the substrate. An epitaxial layer contacts and only covers one of the sidewalls. The other sidewall on the fin element does not contact any epitaxial layer.

公开(公告)号：US09552978B1

公开(公告)日：2017-01-24

申请号：US15059282

申请日：2016-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tong-Jyun Huang ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Jyh-Shyang Jenq ,  Chien-Ting Lin

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/66

CPC classification number: H01L21/02164 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/0223 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02277 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/31056 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of decreasing fin bending, includes providing a substrate including a plurality of fins, wherein a plurality of trenches are defined by the fins, the trenches include a first trench and a second trench, and the second trench is wider than the first trench. Later, a flowable chemical vapor deposition process is performed to form a silicon oxide layer covering the fins, filling up the first trench and partially filling in the second trench. After that, the silicon oxide layer is solidified by a UV curing process. Finally, after the UV curing process, the silicon oxide layer is densified by a steam anneal process.

Abstract translation: 减少翅片弯曲的方法包括提供包括多个翅片的基底，其中由翅片限定多个沟槽，所述沟槽包括第一沟槽和第二沟槽，并且所述第二沟槽比所述第一沟槽更宽。 然后，进行可流动的化学气相沉积工艺以形成覆盖翅片的氧化硅层，填充第一沟槽并部分填充第二沟槽。 之后，氧化硅层通过UV固化工艺固化。 最后，在UV固化过程之后，氧化硅层通过蒸汽退火工艺致密化。

公开(公告)号：US20160276429A1

公开(公告)日：2016-09-22

申请号：US14684445

申请日：2015-04-13

Applicant: United Microelectronics Corp.

Inventor： I-Ming Tseng ,  Wen-An Liang ,  Rai-Min Huang ,  Chen-Ming Huang ,  Tong-Jyun Huang ,  Kuan-Hsien Li

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/7851

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, a spacer layer and a dummy gate structure. The fin shaped structure is disposed on a substrate, wherein the fin shaped structure has a trench. The spacer layer is disposed on sidewalls of the trench. The dummy gate structure is disposed across the trench and includes a portion thereof disposed in the trench.

Abstract translation: 半导体器件及其形成方法，半导体器件包括鳍状结构，间隔层和虚拟栅极结构。 鳍状结构设置在基板上，其中鳍状结构具有沟槽。 间隔层设置在沟槽的侧壁上。 伪栅极结构跨越沟槽设置并且包括其设置在沟槽中的部分。

公开(公告)号：US10090398B2

公开(公告)日：2018-10-02

申请号：US15648439

申请日：2017-07-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rai-Min Huang ,  I-Ming Tseng ,  Tong-Jyun Huang ,  Kuan-Hsien Li

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/308 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78

Abstract: A method of fabricating a patterned structure of a semiconductor device includes the following steps: providing a substrate having a target layer thereon; forming a patterned sacrificial layer on the target layer, wherein the patterned sacrificial layer consists of a plurality of sacrificial features; forming spacers respectively on sidewalls of each of the sacrificial features, wherein all of the spacers are arranged to have a layout pattern; and transferring the layout pattern to the target layer so as to form a first feature and a second feature, wherein the first feature comprises a vertical segment and a horizontal segment, the second feature comprises a vertical segment and a horizontal segment, and a distance between the vertical segment of the first feature and the vertical segment of the second feature is less than a minimum feature size generated by an exposure apparatus.

公开(公告)号：US20170309727A1

公开(公告)日：2017-10-26

申请号：US15648439

申请日：2017-07-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Rai-Min Huang ,  I-Ming Tseng ,  Tong-Jyun Huang ,  Kuan-Hsien Li

IPC: H01L29/66 ,  H01L29/40 ,  H01L27/088 ,  H01L29/06 ,  H01L21/308 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/3086 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/6656 ,  H01L29/785

Abstract: A method of fabricating a patterned structure of a semiconductor device includes the following steps: providing a substrate having a target layer thereon; forming a patterned sacrificial layer on the target layer, wherein the patterned sacrificial layer consists of a plurality of sacrificial features; forming spacers respectively on sidewalls of each of the sacrificial features, wherein all of the spacers are arranged to have a layout pattern; and transferring the layout pattern to the target layer so as to form a first feature and a second feature, wherein the first feature comprises a vertical segment and a horizontal segment, the second feature comprises a vertical segment and a horizontal segment, and a distance between the vertical segment of the first feature and the vertical segment of the second feature is less than a minimum feature size generated by an exposure apparatus.

公开(公告)号：US20160293491A1

公开(公告)日：2016-10-06

申请号：US14696494

申请日：2015-04-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tong-Jyun Huang ,  Rai-Min Huang ,  I-Ming Tseng ,  Kuan-Hsien Li ,  Chen-Ming Huang

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/088 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02271 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653

Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.

Abstract translation: 翅片结构切割过程包括以下步骤。 四个翅片结构形成在基板中，其中包括第一翅片结构，第二翅片结构，第三翅片结构和第四翅片结构的四个翅片结构彼此顺序并联。 执行第一鳍结构切割处理以去除第二鳍结构和第三鳍结构的顶部部分，从而由第二鳍结构形成第一凸起，以及由第三鳍结构形成的第二凸起。 执行第二鳍结构切割处理以完全去除第二凸起和第四鳍结构，但是将第一凸起保持在第一鳍结构旁边。 此外，本发明提供了一种通过所述方法形成的翅片结构。

公开(公告)号：US20150076623A1

公开(公告)日：2015-03-19

申请号：US14025833

申请日：2013-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region.

Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 该方法包括以下步骤：提供具有NMOS区和PMOS区的衬底; 在NMOS区域和PMOS区域分别形成虚拟栅极; 从所述NMOS区域和所述PMOS区域中的每一个去除所述伪栅极; 在NMOS区域和PMOS区域上形成n型功函数层; 去除PMOS区域中的n型功函数层; 在NMOS区域和PMOS区域上形成p型功函数层; 以及在NMOS区域和PMOS区域的p型功函数层上沉积低电阻金属层。

公开(公告)号：US09754938B1

公开(公告)日：2017-09-05

申请号：US15187800

申请日：2016-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Tong-Jyun Huang ,  Shih-Hung Tsai ,  Jia-Rong Wu ,  Tien-Chen Chan ,  Yu-Shu Lin ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate, fin-shaped structures, a protection layer, epitaxial layers, and a gate electrode. The fin-shaped structures are disposed in a first region and a second region of the substrate. The protection layer conformally covers the surface of the substrate and the sidewalls of fin-shaped structures. The epitaxial layers respectively conformally and directly cover the fin-shaped structures in the first region. The gate electrode covers the fin-shaped structures in the second region, and the protection layer is disposed between the gate electrode and the fin-shaped structures.

公开(公告)号：US09466691B2

公开(公告)日：2016-10-11

申请号：US14541107

申请日：2014-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Rai-Min Huang ,  Tong-Jyun Huang ,  Kuan-Hsien Li ,  Chen-Ming Huang

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/265

CPC classification number: H01L29/66537 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

Abstract: A fin shaped structure and a method of forming the same, wherein the method includes forming a fin structure on a substrate. Next, an insulation layer is formed on the substrate and surrounds the fin structure, wherein the insulation layer covers a bottom portion of the fin structure to expose an exposed portion of the fin structure protruded from the insulation layer. Then, a buffer layer is formed on the fin structure. Following this, a threshold voltage implantation process is performed to penetrate through the buffer layer after forming the insulation layer, to form a first doped region on the exposed portion of the fin structure.

Abstract translation: 鳍状结构及其形成方法，其中，所述方法包括在基板上形成翅片结构。 接下来，在衬底上形成绝缘层并围绕鳍结构，其中绝缘层覆盖翅片结构的底部以暴露从绝缘层突出的鳍结构的暴露部分。 然后，在翅片结构上形成缓冲层。 接下来，在形成绝缘层之后，执行阈值电压注入工艺以穿透缓冲层，以在鳍结构的暴露部分上形成第一掺杂区域。

公开(公告)号：US20160141387A1

公开(公告)日：2016-05-19

申请号：US14541107

申请日：2014-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： I-Ming Tseng ,  Rai-Min Huang ,  Tong-Jyun Huang ,  Kuan-Hsien Li ,  Chen-Ming Huang

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L21/308 ,  H01L29/10 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/66537 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

Abstract: A fin shaped structure and a method of forming the same, wherein the method includes forming a fin structure on a substrate. Next, an insulation layer is formed on the substrate and surrounds the fin structure, wherein the insulation layer covers a bottom portion of the fin structure to expose an exposed portion of the fin structure protruded from the insulation layer. Then, a buffer layer is formed on the fin structure. Following this, a threshold voltage implantation process is performed to penetrate through the buffer layer after forming the insulation layer, to form a first doped region on the exposed portion of the fin structure.

Abstract translation: 鳍状结构及其形成方法，其中，所述方法包括在基板上形成翅片结构。 接下来，在衬底上形成绝缘层并围绕鳍结构，其中绝缘层覆盖翅片结构的底部以暴露从绝缘层突出的鳍结构的暴露部分。 然后，在翅片结构上形成缓冲层。 接下来，在形成绝缘层之后，执行阈值电压注入工艺以穿透缓冲层，以在鳍结构的暴露部分上形成第一掺杂区域。