公开(公告)号：US20230270017A1

公开(公告)日：2023-08-24

申请号：US17703967

申请日：2022-03-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Yi Wu ,  Jia-Rong Wu ,  Yu-Hsiang Lin ,  Yi-Wen Chen ,  Kun-Sheng Yang

IPC: H01L43/12 ,  H01L21/308

CPC classification number: H01L43/12 ,  H01L21/308

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a substrate, forming a spin orbit torque (SOT) layer on the MTJ, forming an inter-metal dielectric (IMD) layer around the MTJ and the SOT layer, forming a first hard mask on the IMD layer, forming a semiconductor layer on the first hard mask, and then patterning the first hard mask.

公开(公告)号：US20240347583A1

公开(公告)日：2024-10-17

申请号：US18195905

申请日：2023-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Sheng Yang ,  Yi-Wen Chen ,  Hung-Yi Wu ,  YI CHUEN ENG ,  Yu-Hsiang Lin

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0603 ,  H01L27/0886

Abstract: A semiconductor device includes a substrate having a medium-voltage (MV) region and a logic region, a gate structure on the MV region, a first single diffusion break (SDB) structure and a second SDB structure in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, top surfaces of the first SDB structure and the second SDB structure are coplanar, bottom surfaces of the first SDB structure and the second SDB structure are coplanar, and the first SDB structure and the second SDB structure are made of same material.

公开(公告)号：US09196546B2

公开(公告)日：2015-11-24

申请号：US14025833

申请日：2013-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/76 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A metal gate transistor is disclosed. The metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate. The metal gate further includes a high-k dielectric layer, a bottom barrier metal (BBM) layer on the high-k dielectric layer, a first work function layer on the BBM layer, a second work function layer between the BBM layer and the first work function layer, and a low resistance metal layer on the first work function layer. Preferably, the first work function layer includes a p-type work function layer and the second work function layer includes a n-type work function layer.

Abstract translation: 公开了一种金属栅极晶体管。 金属栅极晶体管包括衬底，衬底上的金属栅极和衬底中的源极/漏极区域。 金属栅极还包括高k电介质层，高k电介质层上的底部阻挡金属（BBM）层，BBM层上的第一功函数层，BBM层和第一层之间的第二功函数层 功函数层，第一功函数层上的低电阻金属层。 优选地，第一功函数层包括p型功函数层，第二功函数层包括n型功函数层。

公开(公告)号：US20160104786A1

公开(公告)日：2016-04-14

申请号：US14543914

申请日：2014-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  En-Chiuan Liou ,  Ssu-I Fu ,  Chi-Mao Hsu ,  Nien-Ting Ho ,  Yu-Ru Yang ,  Yu-Ping Wang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Chien-Chung Huang ,  Tsung-Yin Hsieh ,  Hung-Yi Wu

IPC: H01L29/49 ,  H01L27/092 ,  H01L21/28 ,  H01L21/321 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。

公开(公告)号：US20150076623A1

公开(公告)日：2015-03-19

申请号：US14025833

申请日：2013-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region.

Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 该方法包括以下步骤：提供具有NMOS区和PMOS区的衬底; 在NMOS区域和PMOS区域分别形成虚拟栅极; 从所述NMOS区域和所述PMOS区域中的每一个去除所述伪栅极; 在NMOS区域和PMOS区域上形成n型功函数层; 去除PMOS区域中的n型功函数层; 在NMOS区域和PMOS区域上形成p型功函数层; 以及在NMOS区域和PMOS区域的p型功函数层上沉积低电阻金属层。

公开(公告)号：US09825144B2

公开(公告)日：2017-11-21

申请号：US15644850

申请日：2017-07-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/76 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/423

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.

公开(公告)号：US20170309722A1

公开(公告)日：2017-10-26

申请号：US15644850

申请日：2017-07-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.

公开(公告)号：US09231071B2

公开(公告)日：2016-01-05

申请号：US14187701

申请日：2014-02-24

Applicant: United Microelectronics Corp.

Inventor： Hung-Yi Wu ,  Chien-Ming Lai ,  Yi-Wen Chen

IPC: H01L21/44 ,  H01L21/70 ,  H01L29/49 ,  H01L29/40

CPC classification number: H01L29/4966 ,  H01L29/401 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/78

Abstract: A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes an isolation layer, a gate dielectric layer, a first work function metal, a first bottom barrier layer, a second work function metal, and a first top barrier layer. The isolation layer is formed on a substrate and has a first gate trench. The gate dielectric layer is formed in the first gate trench. The first work function metal is formed on the gate dielectric layer in the first gate trench. The first bottom barrier layer is formed on the first work function metal. The second work function metal is formed on the first bottom barrier layer. The first top barrier layer is formed on the second work function metal.

Abstract translation: 公开了一种半导体结构及其制造方法。 半导体结构包括隔离层，栅介质层，第一功函数金属，第一底阻挡层，第二功函数金属和第一顶阻挡层。 隔离层形成在衬底上并具有第一栅极沟槽。 栅介质层形成在第一栅极沟槽中。 第一功函数金属形成在第一栅极沟槽中的栅介质层上。 第一底部阻挡层形成在第一功函数金属上。 第二功能金属形成在第一底部阻挡层上。 第一顶部阻挡层形成在第二功函数金属上。

公开(公告)号：US09349822B2

公开(公告)日：2016-05-24

申请号：US14543914

申请日：2014-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  En-Chiuan Liou ,  Ssu-I Fu ,  Chi-Mao Hsu ,  Nien-Ting Ho ,  Yu-Ru Yang ,  Yu-Ping Wang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Chien-Chung Huang ,  Tsung-Yin Hsieh ,  Hung-Yi Wu

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/321 ,  H01L27/092

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。

公开(公告)号：US20160035854A1

公开(公告)日：2016-02-04

申请号：US14881162

申请日：2015-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a dummy gate on each of the NMOS region and the PMOS region respectively; removing the dummy gates from each of the NMOS region and the PMOS region; forming a n-type work function layer on the NMOS region and the PMOS region; removing the n-type work function layer in the PMOS region; forming a p-type work function layer on the NMOS region and the PMOS region; and depositing a low resistance metal layer on the p-type work function layer of the NMOS region and the PMOS region.

Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 该方法包括以下步骤：提供具有NMOS区和PMOS区的衬底; 在NMOS区域和PMOS区域分别形成虚拟栅极; 从所述NMOS区域和所述PMOS区域中的每一个去除所述伪栅极; 在NMOS区域和PMOS区域上形成n型功函数层; 去除PMOS区域中的n型功函数层; 在NMOS区域和PMOS区域上形成p型功函数层; 以及在NMOS区域和PMOS区域的p型功函数层上沉积低电阻金属层。