公开(公告)号：US11476192B2

公开(公告)日：2022-10-18

申请号：US16734373

申请日：2020-01-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L23/528 ,  H01L29/08 ,  H01L29/78 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L21/768 ,  H03F3/16 ,  H01L21/321 ,  H01L21/84

Abstract: A semiconductor device includes: a first gate line and a second gate line extending only along a first direction, a third gate line and a fourth gate line extending along the first direction and between the first gate line and the second gate line, a fifth gate line and a sixth gate line extending along a second direction between the first gate line and the second gate line and intersecting the third gate line and the fourth gate line, and first contact plugs on the first gate line. Preferably, the first direction is perpendicular to the second direction and the first gate line and the second gate line are directly connected to the fifth gate line and the sixth gate line.

公开(公告)号：US11462489B2

公开(公告)日：2022-10-04

申请号：US17401335

申请日：2021-08-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/00 ,  H01L27/12 ,  H01L21/84 ,  H01L23/58 ,  H01L23/66 ,  H01L27/06

Abstract: A method of forming integrated circuit device, including: providing a substrate; forming an integrated circuit region on the substrate, the integrated circuit region comprising a dielectric stack; forming a seal ring in the dielectric stack and around a periphery of the integrated circuit region; forming a trench around the seal ring and the trench exposing a sidewall of the dielectric stack; forming a moisture blocking layer continuously covering the integrated circuit region and extending to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack; and forming a passivation layer over the moisture blocking layer.

公开(公告)号：US20220085184A1

公开(公告)日：2022-03-17

申请号：US17068840

申请日：2020-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Heng-Ching Lin ,  Yu-Teng Tseng ,  Chu-Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a main branch extending along a first direction on the substrate and a sub-branch extending along a second direction adjacent to the main branch. The semiconductor device also includes a first doped region overlapping the main branch and the sub-branch according to a top view and a second doped region overlapping the first doped region.

公开(公告)号：US20210359131A1

公开(公告)日：2021-11-18

申请号：US17391048

申请日：2021-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A LDMOS device includes a semiconductor layer on an insulation layer and a ring shape gate on the semiconductor layer. The ring shape gate includes a first gate portion, a second gate portion, and two third gate portions connecting the first gate portion and the second gate portion. The semiconductor device further includes a first drain region and a second drain region formed in the semiconductor layer at two sides of the ring shape gate, a plurality of source regions formed in the semiconductor layer surrounded by the ring shape gate, a plurality of body contact regions formed in the semiconductor layer and arranged between the source regions, and a first body implant region and a second body implant region formed in the semiconductor layer, respectively underlying part of the first gate portion and part of the second gate portion, and being connected by the body contact regions.

公开(公告)号：US20200211899A1

公开(公告)日：2020-07-02

申请号：US16811830

申请日：2020-03-06

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang

IPC: H01L21/8249 ,  H01L21/768 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12 ,  H01L29/66

Abstract: A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device, a bipolar junction transistor (BJT), and a first interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The CMOS device includes an NMOS transistor and a PMOS transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the first side of the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The first interconnect structure is electrically connected to the base at the first side of the substrate and extends to the second side of the substrate.

公开(公告)号：US20200006519A1

公开(公告)日：2020-01-02

申请号：US16054963

申请日：2018-08-03

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/12 ,  H01L21/768

Abstract: A semiconductor structure including a substrate, a complementary metal oxide semiconductor (CMOS) device and a bipolar junction transistor (BJT) is provided. The CMOS device includes an N-type metal oxide semiconductor (NMOS) transistor and a P-type metal oxide semiconductor (PMOS) transistor disposed on the substrate. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. A top surface of a channel of the NMOS transistor, a top surface of a channel of the PMOS transistor and a top surface of the collector of the BJT have the same height. The semiconductor structure can have better overall performance.

公开(公告)号：US10411110B1

公开(公告)日：2019-09-10

申请号：US16053657

申请日：2018-08-02

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

Abstract: A semiconductor structure including a substrate, a BJT, a first interconnect structure and a second interconnect structure is provided. The substrate has a first side and a second side opposite to each other. The BJT is located at the first side. The BJT includes a collector, a base and an emitter. The collector is disposed in the substrate. The base is disposed on the substrate. The emitter is disposed on the base. The first interconnect structure is located at the first side and electrically connected to the base. The second interconnect structure is located at the second side and electrically connected to the collector. The first interconnect structure further extends to the second side. The first interconnect structure and the second interconnect structure are respectively electrically connected to an external circuit at the second side. The semiconductor structure can have better overall performance.

公开(公告)号：US20150221543A1

公开(公告)日：2015-08-06

申请号：US14686784

申请日：2015-04-15

Applicant: United Microelectronics Corp.

Inventor： Tong-Yu Chen ,  Kuo-Yuh Yang

IPC: H01L21/762 ,  H01L21/308 ,  H01L21/265 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3081 ,  H01L21/76232 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/76898 ,  H01L29/0649

Abstract: A method of forming a harmonic-effect-suppression structure is disclosed. The method includes: providing a semiconductor substrate having a base semiconductor substrate, a buried dielectric on the base semiconductor substrate, and a surface semiconductor layer on the buried dielectric. Next, a deep trench is formed extending through the surface semiconductor layer and the buried dielectric into the base semiconductor substrate, a silicon layer is formed within a lower portion of the deep trench, the silicon layer allowed to have a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate, and a dielectric layer is formed within the deep trench and on the silicon layer.

Abstract translation: 公开了一种形成谐波效应抑制结构的方法。 该方法包括：提供具有基底半导体衬底的半导体衬底，基底半导体衬底上的埋入电介质，以及掩埋电介质上的表面半导体层。 接下来，形成深沟槽，其通过表面半导体层和埋入电介质延伸到基底半导体衬底中，在深沟槽的下部形成硅层，硅层允许具有基本相同的顶表面高度 低于基底半导体衬底的顶表面高度，并且在深沟槽内和硅层上形成电介质层。

公开(公告)号：US20150001670A1

公开(公告)日：2015-01-01

申请号：US13932009

申请日：2013-07-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tong-Yu Chen ,  Kuo-Yuh Yang

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3081 ,  H01L21/76232 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/76898 ,  H01L29/0649

Abstract: A semiconductor structure includes a SOI/BOX semiconductor substrate, a device, a deep trench, a silicon layer, and a dielectric layer. The deep trench is adjacent to the device and extends through a shallow trench isolation layer within the SOI layer and the BOX layer and into the base semiconductor substrate. The silicon layer is disposed within a lower portion of the deep trench. The silicon layer has a top surface height substantially the same as or lower than a top surface height of the base semiconductor substrate. The dielectric layer is disposed within the deep trench and on the silicon layer. The deep trench can be formed before or after formation of an interlayer dielectric.

公开(公告)号：US11205609B2

公开(公告)日：2021-12-21

申请号：US16835349

申请日：2020-03-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Pin Hsu ,  Chih-Jung Wang ,  Chu-Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Purakh Raj Verma

IPC: H01L23/482 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L23/485

Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.