公开(公告)号：US10475903B2

公开(公告)日：2019-11-12

申请号：US16258679

申请日：2019-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ling Wang ,  Ping-Hung Chiang ,  Chang-Po Hsiung ,  Chia-Wen Lu ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L27/088 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/06

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

公开(公告)号：US20190157421A1

公开(公告)日：2019-05-23

申请号：US16258679

申请日：2019-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ling Wang ,  Ping-Hung Chiang ,  Chang-Po Hsiung ,  Chia-Wen Lu ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/311 ,  H01L27/088 ,  H01L29/08

Abstract: A transistor with dual spacers includes a gate, a first dual spacer and a second inner spacer. The gate is disposed on a substrate, wherein the gate includes a gate dielectric layer and a gate electrode, and the gate dielectric layer protrudes from the gate electrode and covers the substrate. The first dual spacer is disposed on the gate dielectric layer beside the gate, wherein the first dual spacer includes a first inner spacer and a first outer spacer. The second inner spacer having an L-shaped profile is disposed on the gate dielectric layer beside the first dual spacer. The present invention also provides a method of forming said transistor with dual spacers.

公开(公告)号：US20180233556A1

公开(公告)日：2018-08-16

申请号：US15951966

申请日：2018-04-12

Applicant: United Microelectronics Corp.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Shih-Chieh Pu ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang

IPC: H01L29/06 ,  H01L21/311 ,  H01L27/088 ,  H01L21/762 ,  H01L29/51

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/7621 ,  H01L21/76232 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.