公开(公告)号：US20180233556A1

公开(公告)日：2018-08-16

申请号：US15951966

申请日：2018-04-12

Applicant: United Microelectronics Corp.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Shih-Chieh Pu ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang

IPC: H01L29/06 ,  H01L21/311 ,  H01L27/088 ,  H01L21/762 ,  H01L29/51

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/7621 ,  H01L21/76232 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.

公开(公告)号：US10411088B2

公开(公告)日：2019-09-10

申请号：US15951966

申请日：2018-04-12

Applicant: United Microelectronics Corp.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Shih-Chieh Pu ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/51 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/311

Abstract: A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.

公开(公告)号：US20180102408A1

公开(公告)日：2018-04-12

申请号：US15287535

申请日：2016-10-06

Applicant: United Microelectronics Corp.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Shih-Chieh Pu ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang

IPC: H01L29/06 ,  H01L29/51 ,  H01L21/762 ,  H01L21/311 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/7621 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517

Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.

公开(公告)号：US09577069B1

公开(公告)日：2017-02-21

申请号：US15136982

申请日：2016-04-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chieh Pu ,  Ping-Hung Chiang ,  Chang-Po Hsiung ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang ,  Kuan-Lin Liu

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/308 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L21/02238 ,  H01L21/28123 ,  H01L21/3081 ,  H01L29/0649 ,  H01L29/66575 ,  H01L29/66681

Abstract: A method of fabricating a MOS device is disclosed. A substrate having an active area (AA) silicon portion and shallow trench isolation (STI) region surrounding the active area is provided. A hard mask is formed on the substrate. A portion of the hard mask is removed to form an opening on the AA silicon portion. The opening exposes an edge of the STI region. The AA silicon portion is recessed through the opening to a predetermined depth to form a silicon spacer along a sidewall of the STI region in a self-aligned manner. An oxidation process is performed to oxidize the AA silicon portion and the silicon spacer to form a gate oxide layer.

Abstract translation: 公开了制造MOS器件的方法。 提供了具有有源区（AA）硅部分和围绕有源区的浅沟槽隔离（STI）区的衬底。 在基板上形成硬掩模。 去除硬掩模的一部分以在AA硅部分上形成开口。 开口露出STI区域的边缘。 AA硅部分通过开口凹入预定深度，以自对准的方式沿着STI区域的侧壁形成硅间隔物。 进行氧化处理以氧化AA硅部分和硅间隔物以形成栅极氧化物层。

公开(公告)号：US20190103460A1

公开(公告)日：2019-04-04

申请号：US15720204

申请日：2017-09-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Chia-Lin Wang ,  Chia-Wen Lu ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: A semiconductor transistor device is provided. The semiconductor transistor device includes a semiconductor substrate, a gate structure, a first isolation structure, a first doped region, and a first extra-contact structure. The gate structure is disposed on the semiconductor substrate, and the semiconductor substrate has a first region and a second region respectively located on two opposite sides of the gate structure. The first isolation structure and the first doped region are disposed in the first region of the semiconductor substrate. The first extra-contact structure is disposed on the semiconductor structure. The first extra-contact structure is located between the gate structure and the first doped region and penetrating into the first isolation structure in the first region of the semiconductor substrate, and the first doped region is electrically coupled to the first extra-contact structure.

公开(公告)号：US09972678B2

公开(公告)日：2018-05-15

申请号：US15287535

申请日：2016-10-06

Applicant: United Microelectronics Corp.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Shih-Chieh Pu ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/51 ,  H01L21/762 ,  H01L21/311

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/7621 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517

Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.