公开(公告)号：US20230140347A1

公开(公告)日：2023-05-04

申请号：US17540249

申请日：2021-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ching-Chung Yang

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, an active region in the substrate, a recessed region in the active region, a gate dielectric layer on the recessed region, a gate structure on the gate dielectric layer, and a source/drain region in the active region and at a side of the gate structure. An edge portion of the gate dielectric layer comprises a rounded profile, and the source/drain region directly contacts the edge portion of the gate dielectric layer.

公开(公告)号：US12080794B2

公开(公告)日：2024-09-03

申请号：US18139960

申请日：2023-04-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Nien-Chung Li ,  Chang-Po Hsiung

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7824 ,  H01L29/0649 ,  H01L29/1079 ,  H01L29/517 ,  H01L29/66689

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

公开(公告)号：US09577069B1

公开(公告)日：2017-02-21

申请号：US15136982

申请日：2016-04-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Chieh Pu ,  Ping-Hung Chiang ,  Chang-Po Hsiung ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang ,  Kuan-Lin Liu

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/308 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L21/02238 ,  H01L21/28123 ,  H01L21/3081 ,  H01L29/0649 ,  H01L29/66575 ,  H01L29/66681

Abstract: A method of fabricating a MOS device is disclosed. A substrate having an active area (AA) silicon portion and shallow trench isolation (STI) region surrounding the active area is provided. A hard mask is formed on the substrate. A portion of the hard mask is removed to form an opening on the AA silicon portion. The opening exposes an edge of the STI region. The AA silicon portion is recessed through the opening to a predetermined depth to form a silicon spacer along a sidewall of the STI region in a self-aligned manner. An oxidation process is performed to oxidize the AA silicon portion and the silicon spacer to form a gate oxide layer.

Abstract translation: 公开了制造MOS器件的方法。 提供了具有有源区（AA）硅部分和围绕有源区的浅沟槽隔离（STI）区的衬底。 在基板上形成硬掩模。 去除硬掩模的一部分以在AA硅部分上形成开口。 开口露出STI区域的边缘。 AA硅部分通过开口凹入预定深度，以自对准的方式沿着STI区域的侧壁形成硅间隔物。 进行氧化处理以氧化AA硅部分和硅间隔物以形成栅极氧化物层。

公开(公告)号：US09472661B1

公开(公告)日：2016-10-18

申请号：US14798948

申请日：2015-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Chang-Po Hsiung

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/0653 ,  H01L29/1087 ,  H01L29/404 ,  H01L29/7833

Abstract: A semiconductor structure suitable for operating under a high voltage condition is provided. According to one aspect of the disclosure, the semiconductor structure includes a substrate, a gate, a source region, a drain region and a field-adjusting structure. The gate is disposed on the substrate. The source region and the drain region are disposed in the substrate and at opposite sides of the gate. The field-adjusting structure is disposed on the substrate at an outer side of one of the source region and the drain region. The field-adjusting structure comprises a first portion and a second portion. The second portion is disposed at an outer side of the first portion. The first portion is connected to the gate. The second portion is connected to the one of the source region and the drain region.

Abstract translation: 提供适用于在高电压条件下工作的半导体结构。 根据本公开的一个方面，半导体结构包括衬底，栅极，源极区，漏极区和场调整结构。 栅极设置在基板上。 源极区域和漏极区域设置在衬底中并且在栅极的相对侧。 场调整结构在源极区域和漏极区域之一的外侧设置在衬底上。 场调整结构包括第一部分和第二部分。 第二部分设置在第一部分的外侧。 第一部分连接到门。 第二部分连接到源极区域和漏极区域中的一个。

公开(公告)号：US20230335638A1

公开(公告)日：2023-10-19

申请号：US18139964

申请日：2023-04-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Nien-Chung Li ,  Chang-Po Hsiung

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7824 ,  H01L29/517 ,  H01L29/66689 ,  H01L29/0649 ,  H01L29/1079

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

公开(公告)号：US11682726B2

公开(公告)日：2023-06-20

申请号：US17159166

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Nien-Chung Li ,  Chang-Po Hsiung

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7824 ,  H01L29/0649 ,  H01L29/1079 ,  H01L29/517 ,  H01L29/66689

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

公开(公告)号：US11495681B2

公开(公告)日：2022-11-08

申请号：US17067775

申请日：2020-10-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ching-Chung Yang ,  Shan-Shi Huang ,  Shin-Hung Li ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chiu-Te Lee ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chia-Jung Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28

Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.

公开(公告)号：US20220085210A1

公开(公告)日：2022-03-17

申请号：US17067775

申请日：2020-10-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Ching-Chung Yang ,  Shan-Shi Huang ,  Shin-Hung Li ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chiu-Te Lee ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chia-Jung Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.

公开(公告)号：US11217693B2

公开(公告)日：2022-01-04

申请号：US16711442

申请日：2019-12-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Shin-Hung Li

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor transistor includes a first lightly doped-drain region disposed in a drain region of a semiconductor substrate; a first heavily doped region disposed in the first lightly doped-drain region; and a gate located on the channel region; a gate oxide layer between the gate and the channel region; and a first insulating feature disposed in the first lightly doped-drain region between the channel region and the first heavily doped region. The gate overlaps with the first insulating feature. The thickness of the first insulating feature is greater than that of the gate oxide layer.

公开(公告)号：US20210399132A1

公开(公告)日：2021-12-23

申请号：US16934030

申请日：2020-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung

IPC: H01L29/78 ,  H01L21/8238

Abstract: A buried channel MOSFET includes a dielectric layer, a gate and a buried channel region. The dielectric layer having a recess is disposed on a substrate. The gate is disposed in the recess, wherein the gate includes a first work function metal layer having a “-”shaped cross-sectional profile, and a minimum distance between each sidewalls of the first work function metal layer and the nearest sidewall of the recess is larger than zero. The buried channel region is located in the substrate right below the gate. The present invention provides a method of forming said buried channel MOSFET.