公开(公告)号：US10756128B2

公开(公告)日：2020-08-25

申请号：US16244109

申请日：2019-01-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Shih-Min Chou ,  Ko-Wei Lin ,  Chin-Fu Lin ,  Wei-Chuan Tsai ,  Chun-Yao Yang ,  Chia-Fu Cheng ,  Yi-Syun Chou ,  Wei Chen

IPC: H01L27/14 ,  H01L27/146 ,  H01L21/768 ,  H01L49/02

Abstract: An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.

公开(公告)号：US10734496B2

公开(公告)日：2020-08-04

申请号：US16177368

申请日：2018-10-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/40 ,  H01L27/092

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first bottom barrier metal (BBM) layer on the first region and the second region; forming a first work function metal layer on the first BBM layer on the first region and the second region; removing the first work function metal (WFM) layer and part of the first BBM layer on the second region; and forming a diffusion barrier layer on the first WFM layer on the first region and the first BBM layer on the second region.

公开(公告)号：US20200212090A1

公开(公告)日：2020-07-02

申请号：US16244109

申请日：2019-01-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Shih-Min Chou ,  Ko-Wei Lin ,  Chin-Fu Lin ,  Wei-Chuan Tsai ,  Chun-Yao Yang ,  Chia-Fu Cheng ,  Yi-Syun Chou ,  Wei Chen

IPC: H01L27/146 ,  H01L49/02 ,  H01L21/768

Abstract: An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.

公开(公告)号：US20180261675A1

公开(公告)日：2018-09-13

申请号：US15453351

申请日：2017-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Min Chou ,  Yun-Tzu Chang ,  Wei-Ning Chen ,  Wei-Ming Hsiao ,  Chia-Chang Hsu ,  Kuo-Chih Lai ,  Yang-Ju Lu ,  Yen-Chen Chen ,  Chun-Yao Yang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L21/762 ,  H01L27/088 ,  H01L27/092

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.

公开(公告)号：US10074725B1

公开(公告)日：2018-09-11

申请号：US15453351

申请日：2017-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Min Chou ,  Yun-Tzu Chang ,  Wei-Ning Chen ,  Wei-Ming Hsiao ,  Chia-Chang Hsu ,  Kuo-Chih Lai ,  Yang-Ju Lu ,  Yen-Chen Chen ,  Chun-Yao Yang

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L21/762 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.

公开(公告)号：US20170076995A1

公开(公告)日：2017-03-16

申请号：US14880693

申请日：2015-10-12

Applicant: United Microelectronics Corp.

Inventor： Yun-Tzu Chang ,  Shih-Min Chou ,  Kuo-Chih Lai ,  Ching-Yun Chang ,  Hsiang-Chieh Yen ,  Yen-Chen Chen ,  Yang-Ju Lu ,  Nien-Ting Ho ,  Chi-Mao Hsu

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.

Abstract translation: 提供了一种用于调制具有包括以下步骤的金属栅极结构的半导体器件的功函数的方法。 在基板上设置具有相同结构的第一堆叠栅极结构和第二堆叠栅极结构。 第一堆叠栅极结构和第二堆叠栅极结构分别包括第一类型的第一功函数金属层。 形成图案化的硬掩模层。 图案化的硬掩模层暴露第一堆叠栅极结构的第一功函数金属层并且覆盖第二堆叠栅极结构的第一功函数金属层。 对由图案化的硬掩模层暴露的第一堆叠栅极结构的第一功函数金属层进行第一气体处理。 在第一气体处理中使用的气体包括含氮气体或含氧气体。