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73 条记录 (耗时 0.039 秒)

    Triazines derivatives as cell adhesion inhibitors
    34.
    发明申请
    Triazines derivatives as cell adhesion inhibitors 审中-公开
    三嗪衍生物作为细胞粘附抑制剂

    公开(公告)号：US20060004005A1

    公开(公告)日：2006-01-05

    申请号：US10949096

    申请日：2004-09-24

    申请人： Viswajanani Sattigeri ,  Mohammad Salman ,  Ramamurthi Narayanan ,  Subhendu Seth ,  Simi Sarin ,  Abhijit Ray ,  Sunanda Dastidar

    发明人： Viswajanani Sattigeri ,  Mohammad Salman ,  Ramamurthi Narayanan ,  Subhendu Seth ,  Simi Sarin ,  Abhijit Ray ,  Sunanda Dastidar

    IPC分类号： A61K31/53

    CPC分类号： C07D251/52 ,  C07D251/16 ,  C07D251/18 ,  C07D251/50 ,  C07D251/54 ,  C07D251/70 ,  C07D405/12 ,  C07D409/12

    摘要： The present invention relates to triazine derivatives as cell adhesion inhibitors. The compounds of this invention can be useful inter alia, for inhibition and prevention of cell adhesion and cell adhesion-mediated pathologies, including inflammatory and autoimmune diseases such as bronchial asthma, rheumatoid arthritis, type I diabetes, multiple sclerosis, allograft rejection, psoriasis. The compounds can be used to formulate pharmacological compositions, and the methods of treating bronchial asthma, rheumatoid arthritis, multiple sclerosis, type I diabetes, psoriasis, allograft rejection, and other inflammatory and/or autoimmune disorders, using the compounds are also provided herein.

    摘要翻译： 本发明涉及作为细胞粘附抑制剂的三嗪衍生物。 本发明的化合物尤其可用于抑制和预防细胞粘附和细胞粘附介导的病理学，包括炎症和自身免疫性疾病如支气管哮喘，类风湿性关节炎，I型糖尿病，多发性硬化，同种异体移植排斥，牛皮癣。 该化合物可用于配制药物组合物，本文还提供了使用该化合物治疗支气管哮喘，类风湿性关节炎，多发性硬化，I型糖尿病，牛皮癣，同种异体移植排斥和其它炎性和/或自身免疫性疾病的方法。

    High speed output buffer for high/low voltage operation
    35.
    发明授权
    High speed output buffer for high/low voltage operation 有权
    用于高/低压运行的高速输出缓冲器

    公开(公告)号：US06225824B1

    公开(公告)日：2001-05-01

    申请号：US09264433

    申请日：1999-03-08

    申请人： R Madhu ,  Abhijit Ray

    发明人： R Madhu ,  Abhijit Ray

    IPC分类号： H03K1902

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

    摘要： An output buffer (500) is disclosed that includes an output driver circuit (508) having a first drive transistor (P504) for driving an output node (520) to a first logic level according the potential at a first pre-drive node (516), and a second drive transistor (N504) for driving the output node (520) to a second logic level according the potential at a second pre-drive node (518). The potential at the first pre-drive node (516) is established by a first standard pre-drive circuit (504) and a first phased pre-drive circuit (512). The potential at the second pre-drive node (518) is established by a second standard pre-drive circuit (506) and a second phased pre-drive circuit (514). In a low voltage mode of operation, where the rate of current drawn (di/dt) by the output driver circuit (508) is reduced, the standard and phased pre-drive circuits (504, 506, 512, 514) function together to drive their respective pre-drive nodes. In a high voltage mode of operation, where output driver circuit (508) di/dt is increased, the phased pre-drive circuits (512 and 514) are enabled a predetermined delay after the standard pre-drive circuits (504 and 506).

    摘要翻译： 公开了一种输出缓冲器（500），其包括具有第一驱动晶体管（P504）的输出驱动器电路（508），用于根据第一预驱动节点（516）处的电位将输出节点（520）驱动到第一逻辑电平 ）和用于根据第二预驱动节点（518）处的电位将输出节点（520）驱动到第二逻辑电平的第二驱动晶体管（N504）。 第一预驱动节点（516）处的电位由第一标准预驱动电路（504）和第一定相预驱动电路（512）建立。 第二预驱动节点（518）处的电位由第二标准预驱动电路（506）和第二定相预驱动电路（514）建立。 在低电压工作模式中，由输出驱动器电路（508）引出的电流（di / dt）的速率减小，标准和相位预驱动电路（504,506,512,514）一起工作 驱动各自的预驱动器节点。 在高电压工作模式下，在输出驱动器电路（508）di / dt增加的情况下，相位预驱动电路（512和514）在标准预驱动电路（504和506）之后能够预定的延迟。

    Switching circuits and methods for programmable logic devices
    36.
    发明授权
    Switching circuits and methods for programmable logic devices 失效
    用于可编程逻辑器件的开关电路和方法

    公开(公告)号：US07629812B2

    公开(公告)日：2009-12-08

    申请号：US11888977

    申请日：2007-08-03

    申请人： Damodar R. Thummalapally ,  Abhijit Ray

    发明人： Damodar R. Thummalapally ,  Abhijit Ray

    IPC分类号： H03K19/173

    CPC分类号： H01L27/11803 ,  H01L27/098 ,  H01L29/808 ,  H03K19/17736 ,  H03K19/1778

    摘要： A switching circuit can have a plurality of first signal lines of a programmable logic device, a plurality of second signal lines of the programmable logic device, and a plurality of switch elements. Each switch element can selectively couple one first signal line to a second signal line and include one or more switch junction field effect transistors (JFETs) having a first control gate separated from a second control gate by a channel region.

    摘要翻译： 开关电路可以具有可编程逻辑器件的多条第一信号线，可编程逻辑器件的多条第二信号线以及多个开关元件。 每个开关元件可选择性地将一个第一信号线耦合到第二信号线，并且包括具有通过沟道区与第二控制栅极分离的第一控制栅极的一个或多个开关结场效应晶体管（JFET）。

    Device and Method for Continuity of Care in a Health Care Environment
    39.
    发明申请
    Device and Method for Continuity of Care in a Health Care Environment 审中-公开
    在医疗保健环境中保持关怀的设备和方法

    公开(公告)号：US20080215372A1

    公开(公告)日：2008-09-04

    申请号：US12041637

    申请日：2008-03-03

    申请人： Abhijit Ray

    发明人： Abhijit Ray

    IPC分类号： G06F19/00

    CPC分类号： G06Q50/24 ,  G16H10/65

    摘要： The present invention is directed to a method and device for ensuring patient continuity of care. One aspect of the present method includes providing to a patient a hand-held portable device that has at least a portion of the patient's medical record stored thereon. The patient can then carry the hand-held portable device on his person for access of the information thereon whenever necessary or desired.

    摘要翻译： 本发明涉及一种用于确保患者的护理连续性的方法和装置。 本方法的一个方面包括向患者提供具有存储在其上的患者医疗记录的至少一部分的手持便携式设备。 然后，病人随身携带手持式便携式设备，以便在需要或期望的情况下存取其上的信息。

    Delay settings for a wide-range, high-precision delay-locked loop and a delay locked loop implementation using these settings
    40.
    发明授权
    Delay settings for a wide-range, high-precision delay-locked loop and a delay locked loop implementation using these settings 失效
    使用这些设置可实现宽范围，高精度延迟锁定环和延迟锁定环实现的延迟设置

    公开(公告)号：US07027548B1

    公开(公告)日：2006-04-11

    申请号：US09873016

    申请日：2001-05-30

    申请人： Chaitanya Palusa ,  Abhijit Ray

    发明人： Chaitanya Palusa ,  Abhijit Ray

    IPC分类号： H03D3/24

    CPC分类号： H03L7/0812 ,  H03D13/004 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/10

    摘要： A delay-locked-loop (DLL) that has increased precision and a wide range of operation is formed by utilizing a chain of delay blocks to add or subtract a discreet amount of delay, and a voltage-controlled delay line (VCDL) to add or subtract a smaller amount of delay. The delay blocks allow the delayed clock signal to get close to the reference clock signal, while the VCDL allows the delayed clock signal to lock onto the reference clock signal.

    摘要翻译： 通过利用一系列延迟块来增加或减少一定的延迟量来形成具有增加的精度和较宽的操作范围的延迟锁定环（DLL），以及电压控制的延迟线（VCDL）来添加 或减去较小的延迟量。 延迟块允许延迟的时钟信号接近参考时钟信号，而VCDL允许延迟的时钟信号锁定到参考时钟信号。