公开(公告)号：US06560677B1

公开(公告)日：2003-05-06

申请号：US09304664

申请日：1999-05-04

申请人： Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

发明人： Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

IPC分类号： G06F1208

CPC分类号： G06F9/30043 ,  G06F12/0864 ,  G06F12/121 ,  G06F12/126 ,  G06F12/128

摘要： Ways of a cache memory system are designated as being in one of three subsets: a normal subset, a transient subset, and a locked subset. The designation of the respective subsets is provided by a normal subset floor index, a transient subset floor index, and a transient subset ceiling index. The respective indexes are used to select the subset into which new entries are copied from main memory as a result of a cache miss. If the new entry is designated as being characterized by normal program behavior, it is copied into the normal subset in the cache. If the new entry is designated as being characterized by transient program behavior, it is copied into the transient subset in the cache. The relationship between the normal subset and the transient subset is programmable. For example, the normal and the transient subsets may include at least one common way of the cache memory or the transient subset may be completely included in the normal subset or completely separate therefrom.

摘要翻译： 缓存存储器系统的方式被指定为三个子集之一：正常子集，瞬变子集和锁定子集。 相应子集的指定由正常子集层索引，瞬时子集底层索引和瞬时子集上限索引提供。 相应的索引用于选择由于高速缓存未命中而从主存储器复制新条目的子集。 如果新条目被指定为通过正常程序行为表征，则将其复制到缓存中的正常子集中。 如果新条目被指定为由瞬时程序行为表征，则将其复制到缓存中的瞬态子集中。 正常子集与瞬态子集之间的关系是可编程的。 例如，正常和瞬态子集可以包括高速缓冲存储器的至少一种常见方式，或者瞬态子集可以完全包含在正常子集中或与其完全分开。

公开(公告)号：US6081860A

公开(公告)日：2000-06-27

申请号：US975545

申请日：1997-11-20

申请人： Jeffrey Todd Bridges ,  Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer

发明人： Jeffrey Todd Bridges ,  Juan Guillermo Revilla ,  Thomas Andrew Sartorius ,  Mark Michael Schaffer

IPC分类号： G06F13/364 ,  G06F13/00

CPC分类号： G06F13/364

摘要： A process and system for transferring data including at least one slave device connected to at least one master device through an arbiter device. The master and slave devices are connected by a single address bus, a write data bus and a read data bus. The arbiter device receives requests for data transfers from the master devices and selectively transmits the requests to the slave devices. The master devices and the slave devices are further connected by a plurality of transfer qualifier signals which may specify predetermined characteristics of the requested data transfers. Control signals are also communicated between the arbiter device and the slave devices to allow appropriate slave devices to latch addresses of requested second transfers during the pendency of current or primary data transfers so as to obviate an address transfer latency typically required for the second transfer. The design is configured to advantageously function in mixed systems which may include address-pipelining and non-address-pipelining slave devices.

摘要翻译： 一种用于传送数据的过程和系统，包括通过仲裁设备连接到至少一个主设备的至少一个从设备。 主设备和从设备通过单个地址总线，写数据总线和读数据总线连接。 仲裁设备接收来自主设备的数据传输请求，并选择性地将请求发送到从设备。 主设备和从设备通过可以指定所请求的数据传输的预定特性的多个传输限定符信号进一步连接。 控制信号也在仲裁设备和从设备之间通信，以允许适当的从设备在当前或主要数据传输的未决期间锁存所请求的第二传送的地址，以便消除通常为第二传送所需的地址传输等待时间。 该设计被配置为有利地在可以包括地址流水线和非地址流水线从设备的混合系统中起作用。

公开(公告)号：US5809293A

公开(公告)日：1998-09-15

申请号：US283128

申请日：1994-07-29

申请人： Jeffrey Todd Bridges ,  Thomas K. Collopy ,  James N. Dieffenderfer ,  Thomas Joseph Irene ,  Harry I. Linzer ,  Thomas Andrew Sartorius

发明人： Jeffrey Todd Bridges ,  Thomas K. Collopy ,  James N. Dieffenderfer ,  Thomas Joseph Irene ,  Harry I. Linzer ,  Thomas Andrew Sartorius

IPC分类号： G06F11/34 ,  G06F11/36 ,  G06F9/00

CPC分类号： G06F11/3636 ,  G06F11/3466 ,  G06F11/3648 ,  G06F2201/865

摘要： A system and method for tracing program code within a processor having an embedded cache memory. The non-invasive tracing technique minimizes the need for trace information to be broadcast externally. The tracing technique monitors changes in instruction flow from the normal execution stream of the code. The tracing technique monitors the updating of processor branch target register contents in order to monitor branch target flow of the code. A FIFO and serial logic circuitry is utilized to minimize the number of chip pins required to broadcast the information from the chip. The tracing technique utilizes instruction and data breakpoint debug functions to signal an external trace tool that a trace event has occurred.

摘要翻译： 一种用于在具有嵌入式高速缓冲存储器的处理器内跟踪程序代码的系统和方法。 非侵入性跟踪技术最大限度地减少了要在外部广播的跟踪信息的需要。 跟踪技术监视来自代码的正常执行流的指令流程的变化。 跟踪技术监控处理器分支目标寄存器内容的更新，以便监视代码的分支目标流。 使用FIFO和串行逻辑电路来最小化从芯片广播信息所需的芯片引脚数。 跟踪技术利用指令和数据断点调试功能来发出跟踪事件发生的外部跟踪工具。

公开(公告)号：US20090313695A1

公开(公告)日：2009-12-17

申请号：US12485089

申请日：2009-06-16

申请人： Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Steven M. Millendorf

发明人： Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Steven M. Millendorf

IPC分类号： G06F12/14

CPC分类号： G06F12/145 ,  G06F12/1027 ,  G06F21/52 ,  G06F21/54 ,  G06F21/575 ,  G06F21/629 ,  G06F21/71 ,  G06F21/74 ,  G06F21/79 ,  G06F21/81 ,  G06F2221/2105 ,  G06F2221/2141

摘要： Methods and systems to guard against attacks designed to replace authenticated, secure code with non-authentic, unsecure code and using existing hardware resources in the CPU's memory management unit (MMU) are disclosed. In certain embodiments, permission entries indicating that pages in memory have been previously authenticated as secure are maintained in a translation lookaside buffer (TLB) and checked upon encountering an instruction residing at an external page. A TLB permission entry indicating permission is invalid causes on-demand authentication of the accessed page. Upon authentication, the permission entry in the TLB is updated to reflect that the page has been authenticated. As another example, in certain embodiments, a page of recently authenticated pages is maintained and checked upon encountering an instruction residing at an external page.

摘要翻译： 公开了用于防止旨在用非真实的，不安全的代码替换已认证的安全代码并且使用CPU的存储器管理单元（MMU）中的现有硬件资源的攻击的方法和系统。 在某些实施例中，指示存储器中的页面已经被先前认证为安全的许可条目保持在翻译后备缓冲器（TLB）中，并且在遇到驻留在外部页面上的指令时进行检查。 指示许可的TLB许可条目是无效的，导致访问页面的按需认证。 认证后，TLB中的许可条目被更新以反映该页面已被认证。 作为另一示例，在某些实施例中，在遇到驻留在外部页面上的指令时，维护和检查最近被认证的页面的页面。

公开(公告)号：US07152155B2

公开(公告)日：2006-12-19

申请号：US11061981

申请日：2005-02-18

申请人： Michael Scott McIlvaine ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

发明人： Michael Scott McIlvaine ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

IPC分类号： G06F9/38

CPC分类号： G06F9/3844 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3861

摘要： When a branch misprediction in a pipelined processor is discovered, if the mispredicted branch instruction is not the last uncommitted instruction in the pipelines, older uncommitted instructions are checked for dependency on a long latency operation. If one is discovered, all uncommitted instructions are flushed from the pipelines without waiting for the dependency to be resolved. The branch prediction is corrected, and the branch instruction and all flushed instructions older than the branch instruction are re-fetched and executed.

摘要翻译： 当发现流水线处理器中的分支错误预测时，如果错误的分支指令不是管道中的最后一条未提交的指令，则会检查较长的未提交的指令对长时间延迟操作的依赖性。 如果被发现，所有未提交的指令都将从管道中刷新，而不必等待解决依赖关系。 纠正分支预测，并且重新获取并执行分支指令和比分支指令更早的所有刷新指令。

公开(公告)号：US08639943B2

公开(公告)日：2014-01-28

申请号：US12485089

申请日：2009-06-16

申请人： Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Steven M. Millendorf

发明人： Jeffrey Todd Bridges ,  Thomas Andrew Sartorius ,  Steven M. Millendorf

IPC分类号： G06F11/30 ,  G06F12/14

CPC分类号： G06F12/145 ,  G06F12/1027 ,  G06F21/52 ,  G06F21/54 ,  G06F21/575 ,  G06F21/629 ,  G06F21/71 ,  G06F21/74 ,  G06F21/79 ,  G06F21/81 ,  G06F2221/2105 ,  G06F2221/2141

摘要： Methods and systems to guard against attacks designed to replace authenticated, secure code with non-authentic, unsecure code and using existing hardware resources in the CPU's memory management unit (MMU) are disclosed. In certain embodiments, permission entries indicating that pages in memory have been previously authenticated as secure are maintained in a translation lookaside buffer (TLB) and checked upon encountering an instruction residing at an external page. A TLB permission entry indicating permission is invalid causes on-demand authentication of the accessed page. Upon authentication, the permission entry in the TLB is updated to reflect that the page has been authenticated. As another example, in certain embodiments, a page of recently authenticated pages is maintained and checked upon encountering an instruction residing at an external page.

摘要翻译： 公开了用于防止旨在用非真实的，不安全的代码替换已认证的安全代码并且使用CPU的存储器管理单元（MMU）中的现有硬件资源的攻击的方法和系统。 在某些实施例中，指示存储器中的页面已经被先前认证为安全的许可条目保持在翻译后备缓冲器（TLB）中，并且在遇到驻留在外部页面上的指令时进行检查。 指示许可的TLB许可条目是无效的，导致访问页面的按需认证。 认证后，TLB中的许可条目被更新以反映该页面已被认证。 作为另一示例，在某些实施例中，在遇到驻留在外部页面上的指令时，维护和检查最近被认证的页面的页面。

公开(公告)号：US07281118B2

公开(公告)日：2007-10-09

申请号：US11198042

申请日：2005-08-05

申请人： Jeffrey Todd Bridges ,  Gordon Taylor Davis ,  Thomas Andrew Sartorius ,  Michael Steven Siegel

发明人： Jeffrey Todd Bridges ,  Gordon Taylor Davis ,  Thomas Andrew Sartorius ,  Michael Steven Siegel

IPC分类号： G06F15/167

CPC分类号： G06F13/28

摘要： A method and system for messaging between processors and co-processors connected through a bus. The method permits a multi-thread system processor to request the services of a processor or co-processor located on the bus. Message control blocks are stored in a memory which identify the physical address of the target processor, as well as a memory location in the memory dedicated to the thread requesting the service. When the system processor requests service of a processor or co-processor, a DCR command is created pointing to the message control block. A message is built from information contained in the message control block or transferred to the processor or co-processor. The return address for the processor or co-processor message is concatenated with the thread number, so that the processor or co-processor can create a return message specifically identifying memory space dedicated to the requesting thread for storage of the response message.

摘要翻译： 用于通过总线连接的处理器和协处理器之间的消息传递的方法和系统。 该方法允许多线程系统处理器请求位于总线上的处理器或协处理器的服务。 消息控制块存储在识别目标处理器的物理地址的存储器中，以及专用于请求服务的线程的存储器中的存储器位置。 当系统处理器请求处理器或协处理器的服务时，创建指向消息控制块的DCR命令。 消息由消息控制块中包含的信息构建或传送到处理器或协处理器。 处理器或协处理器消息的返回地址与线程号连接，使得处理器或协处理器可以创建专用于识别请求线程的存储空间的返回消息以存储响应消息。

公开(公告)号：US09710269B2

公开(公告)日：2017-07-18

申请号：US11336357

申请日：2006-01-20

申请人： James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius

发明人： James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius

IPC分类号： G06F9/30

CPC分类号： G06F9/30072 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/3016 ,  G06F9/30167

摘要： Delays due to waiting for operands that will not be used by a select operand instruction, are alleviated based on an early recognition that such operand data is not required in order to complete the processing of the select operand instruction. At appropriate points prior to execution, determinations are made regarding a selection criterion or criteria specified by the select operand instruction, conditions that affect the selection criteria, and the availability of operands. A hold circuit uses the determinations to control the activation and release of a hold signal that controls processor pipeline stalls. A stall required to wait for operand data is skipped or a stall is terminated early, if the selected operand is available even though the other operand, that will not be used, is not available. A stall due to waiting for operands is maintained until the selection criteria is met and the selected operand is fetched and made available.

公开(公告)号：US07263577B2

公开(公告)日：2007-08-28

申请号：US11072849

申请日：2005-03-03

申请人： Jeffrey Todd Bridges ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius

发明人： Jeffrey Todd Bridges ,  James Norris Dieffenderfer ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius

IPC分类号： G06F12/00

CPC分类号： G06F9/30058 ,  G06F1/3203 ,  G06F1/3275 ,  G06F9/384 ,  Y02D10/13 ,  Y02D10/14

摘要： A renaming register file complex for saving power is described. A mapping unit transforms an instruction register number (IRN) to a logical register number (LRN). The renaming register file maps an LRN to a physical register number (PRN), there being a greater number of physical registers than addressable by direct use of the IRN. The renaming register file uses a content addressable memory (CAM) to provide the mapping function. The renaming register file CAM further uses current processor state information to selectively enable tag comparators to minimize power in accessing registers. When a tag comparator is not enabled it remains in a low power state. A processor using a renaming register file with low power features is also described.

摘要翻译： 描述了一种用于节省电力的重命名寄存器文件。 映射单元将指令寄存器号（IRN）变换为逻辑寄存器号（LRN）。 重命名寄存器文件将LRN映射到物理寄存器编号（PRN），通过直接使用IRN，存在比可寻址的更大数量的物理寄存器。 重命名寄存器文件使用内容可寻址存储器（CAM）来提供映射功能。 重命名寄存器文件CAM还使用当前处理器状态信息来选择性地使标签比较器最小化访问寄存器的功率。 当标签比较器未使能时，它保持在低功率状态。 还描述了使用具有低功率特征的重命名寄存器文件的处理器。

公开(公告)号：US07805588B2

公开(公告)日：2010-09-28

申请号：US11254873

申请日：2005-10-20

申请人： Jeffrey Todd Bridges ,  James Norris Dieffenderfer ,  Thomas Sartorius ,  Brian Michael Stempel ,  Rodney Wayne Smith

发明人： Jeffrey Todd Bridges ,  James Norris Dieffenderfer ,  Thomas Sartorius ,  Brian Michael Stempel ,  Rodney Wayne Smith

IPC分类号： G06F12/00

CPC分类号： G06F12/1063 ,  G06F12/1054 ,  G06F12/145 ,  Y02D10/13

摘要： A processing system may include a memory configured to store data in a plurality of pages, a TLB, and a memory cache including a plurality of cache lines. Each page in the memory may include a plurality of lines of memory. The memory cache may permit, when a virtual address is presented to the cache, a matching cache line to be identified from the plurality of cache lines, the matching cache line having a matching address that matches the virtual address. The memory cache may be configured to permit one or more page attributes of a page located at the matching address to be retrieved from the memory cache and not from the TLB, by further storing in each one of the cache lines a page attribute of the line of data stored in the cache line.

摘要翻译： 处理系统可以包括被配置为在多个页面中存储数据的存储器，TLB和包括多个高速缓存行的存储器高速缓存。 存储器中的每个页面可以包括多行存储器。 当虚拟地址被呈现给高速缓存时，存储器高速缓存可以允许要从多条高速缓存行识别的匹配高速缓存行，匹配高速缓存行具有与虚拟地址匹配的匹配地址。 存储器高速缓存可以被配置为允许通过在高速缓存行的每一个中存储行的页面属性来允许位于匹配地址的页面的一个或多个页面属性从存储器高速缓存而不是从TLB检索， 的数据存储在缓存行中。