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    Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge
    31.
    发明授权
    Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge 失效
    通过在栅极边缘形成微动开关来形成低重叠电容晶体管的方法

    公开(公告)号：US06417056B1

    公开(公告)日：2002-07-09

    申请号：US09981439

    申请日：2001-10-18

    申请人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

    发明人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

    IPC分类号： H01L21336

    CPC分类号： H01L29/66636 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834

    摘要： A method for forming a transistor having low overlap capacitance by forming a microtrench at the gate edge to reduce effective dielectric constant is described. A gate electrode is provided overlying a gate dielectric layer on a substrate and having a hard mask layer thereover. An oxide layer is formed overlying the substrate. First spacers are formed on sidewalls of the gate electrode and overlying the oxide layer. Source/drain extensions are implanted. Second spacers are formed on the first spacers. Source/drain regions are implanted. A dielectric layer is deposited overlying the gate electrode and the oxide layer and planarized to the hard mask layer whereby the first and second spacers are exposed. The exposed second spacers and underlying oxide layer are removed. The exposed substrate underlying the second spacers is etched into to form a microtrench undercutting the gate oxide layer at an edge of the gate electrode. The microtrench is filled with an epitaxial oxide layer and planarized to the hard mask layer. The dielectric layer is patterned to form third spacers on the epitaxial oxide layer. The microtrench reduces the effective dielectric constant at the overlap between the gate and the source/drain extensions to complete formation of a transistor having low overlap capacitance.

    摘要翻译： 描述了通过在栅极边缘处形成微通孔以形成具有低重叠电容的晶体管以降低有效介电常数的方法。 栅电极被设置在衬底上的栅介电层上，并且在其上具有硬掩模层。 在衬底上形成氧化物层。 第一间隔物形成在栅电极的侧壁上并覆盖氧化物层。 源/漏扩展被植入。 第二间隔件形成在第一间隔件上。 源极/漏极区域被植入。 沉积覆盖在栅电极和氧化物层上的介电层，并且平坦化到硬掩模层，由此使第一和第二间隔物暴露。 去除暴露的第二间隔物和下面的氧化物层。 蚀刻第二间隔物下面的暴露的基底以形成在栅电极的边缘处切割栅极氧化物层的微切口。 微通孔填充有外延氧化物层并且平坦化到硬掩模层。 图案化电介质层以在外延氧化物层上形成第三间隔物。 微通道减小栅极和源极/漏极延伸部之间的重叠处的有效介电常数，以完成具有低重叠电容的晶体管的形成。

    Method for forming a transistor gate dielectric with high-K and low-K regions
    32.
    发明授权
    Method for forming a transistor gate dielectric with high-K and low-K regions 有权
    用于形成具有高K和低K区的晶体管栅极电介质的方法

    公开(公告)号：US06406945B1

    公开(公告)日：2002-06-18

    申请号：US09769810

    申请日：2001-01-26

    申请人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

    发明人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

    IPC分类号： H01L21335

    CPC分类号： H01L29/517 ,  H01L21/28167 ,  H01L21/28194 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/518 ,  H01L29/66583 ,  Y10S257/90

    摘要： A method for forming a gate dielectric having regions with different dielectric constants. A dummy dielectric layer is formed over a semiconductor structure. The dummy dielectric layer is patterned to form a gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the gate opening. A low-K dielectric layer is formed on the high-K dielectric layer. Spacers are formed on the low-K dielectric layer at the edges of the gate opening. The low-K dielectric layer is removed from the bottom of the gate opening between the spacers. The spacers are removed to form a stepped gate opening. The stepped gate opening has both a high-K dielectric layer and a low-K dielectric layer on the sidewalls and at the edges of the bottom of the gate opening and only a high-k dielectric layer in the center of the bottom of the stepped gate opening. A gate electrode is formed in the stepped gate opening.

    摘要翻译： 一种形成具有不同介电常数区域的栅极电介质的方法。 在半导体结构上形成虚拟电介质层。 图案化虚拟介质层以形成栅极开口。 在虚拟电介质上和栅极开口中形成高K电介质层。 在高K电介质层上形成低K电介质层。 在栅极开口边缘的低K电介质层上形成间隔物。 低K电介质层从间隔物之间​​的栅极开口的底部去除。 移除间隔件以形成阶梯式门开口。 阶梯式门开口在侧壁和栅极开口底部的边缘处具有高K电介质层和低K电介质层，并且仅在台阶底部中心的高k电介质层 开门 在阶梯式门开口形成栅电极。

    Method for forming PLDD structure with minimized lateral dopant diffusion
    33.
    发明授权
    Method for forming PLDD structure with minimized lateral dopant diffusion 失效
    用最小化横向掺杂剂扩散形成PLDD结构的方法

    公开(公告)号：US06312999B1

    公开(公告)日：2001-11-06

    申请号：US09819378

    申请日：2001-03-29

    申请人： Subrahamanyam Chivukula ,  Yelehanka Ramachandramurthy Pradeep ,  Madhusudan Mukhopdhyay ,  Palanivel Balasubramaniam

    发明人： Subrahamanyam Chivukula ,  Yelehanka Ramachandramurthy Pradeep ,  Madhusudan Mukhopdhyay ,  Palanivel Balasubramaniam

    IPC分类号： H01L21336

    CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/7833

    摘要： A method for forming a MOSFET having an LDD structure with minimal lateral dopant diffusion is described. A gate electrode is provided overlying a gate dielectric layer on a semiconductor substrate. Dielectric spacers are formed on sidewalls of the gate electrode. Source and drain regions are formed associated with the gate electrode. The gate electrode and source and drain regions are silicided. Thereafter, the spacers are removed to expose the semiconductor substrate. LDD regions are formed using plasma doping in the exposed semiconductor substrate between the source and drain regions and the gate electrode to complete formation of an LDD structure in the fabrication of an integrated circuit device.

    摘要翻译： 描述了一种用于形成具有最小横向掺杂剂扩散的LDD结构的MOSFET的方法。 栅电极被设置在半导体衬底上的栅介电层上。 电介质隔板形成在栅电极的侧壁上。 源极和漏极区域形成为与栅电极相关联。 栅电极和源极和漏极区域被硅化。 此后，去除间隔物以露出半导体衬底。 在源极和漏极区域和栅电极之间的暴露的半导体衬底中使用等离子体掺杂形成LDD区域，以在集成电路器件的制造中完成LDD结构的形成。

    Method for forming a T-gate for better salicidation
    34.
    发明授权
    Method for forming a T-gate for better salicidation 有权
    用于形成更好的盐析的T型门的方法

    公开(公告)号：US06284613B1

    公开(公告)日：2001-09-04

    申请号：US09434920

    申请日：1999-11-05

    申请人： Chivukula Subrahmanyam ,  Yelehanka Ramachandramurthy Pradeep ,  Ramakrishnan Rajagopal

    发明人： Chivukula Subrahmanyam ,  Yelehanka Ramachandramurthy Pradeep ,  Ramakrishnan Rajagopal

    IPC分类号： H01L21336

    CPC分类号： H01L29/6659 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7836

    摘要： A method for a T-gate and salicide process that allows narrow bottom gate widths below 0.25 &mgr;m and wide top gate widths to allow silicide gate contacts on the top of the T-gate. A dummy gate composed of an insulating material is formed over the substrate. Then we form LDD regions adjacent to the dummy gate preferably by ion implanting f (I/I) impurity ions into the substrate using the dummy gate as a mask. A pad oxide layer and dielectric layer are formed over the substrate surface. The dielectric layer over the dummy gate is removed preferably by a CMP process. We then remove the dummy gate to form a gate opening exposing the substrate surface. A gate dielectric layer is formed over the substrate surface in the gate opening. We form a polysilicon layer over the dielectric layer and the substrate surface in the gate opening. The polysilicon layer is patterned to form a T-gate. The dielectric layer is removed. We forming source/drain (S/D) regions adjacent to the T-gate by an Ion implant process. A silicide layer is formed over the T-gate and the substrate to form silicide contacts to the SID regions and gate contacts to the T-gate. Then we form a dielectric layer (ILD) over the T-gate and substrate. We form contact opening through the dielectric layer to expose the S/D regions and T-gate. We form contacts to the S/D regions and to the T-gate.

    摘要翻译： 一种用于T栅极和自对准硅化物工艺的方法，其允许窄的底栅宽度低于0.25μm和宽的顶栅宽度以允许在T栅极的顶部上的硅化物栅极接触。 在衬底上形成由绝缘材料构成的虚拟栅极。 然后，使用伪栅极作为掩模，优选通过将f（I / I）杂质离子注入到衬底中来形成与虚拟栅极相邻的LDD区域。 在衬底表面上形成衬垫氧化物层和电介质层。 虚拟栅极上的电介质层优选地通过CMP工艺去除。 然后我们去除虚拟栅极以形成露出衬底表面的栅极开口。 在栅极开口中的衬底表面上形成栅极电介质层。 我们在电介质层和栅极开口中的衬底表面上形成多晶硅层。 图案化多晶硅层以形成T形栅极。 去除电介质层。 我们通过离子注入工艺形成与T型栅极相邻的源极/漏极（S / D）区域。 在T栅极和衬底之上形成硅化物层，以形成与SID区的硅化物接触和到T栅极的栅极接触。 然后我们在T栅极和衬底上形成介电层（ILD）。 我们通过介电层形成接触开口以暴露S / D区域和T型栅极。 我们与S / D区域和T型门形成联系。

    Semiconductor local interconnect and contact
    35.
    发明申请
    Semiconductor local interconnect and contact 有权
    半导体局部互连和接触

    公开(公告)号：US20050130402A1

    公开(公告)日：2005-06-16

    申请号：US11045202

    申请日：2005-01-27

    申请人： Yelehanka Ramachandramurthy Pradeep ,  Tong Chen ,  Zhi Han ,  Zhen Zheng ,  Kelvin Ong ,  Tian Gu ,  Syn Cheah

    发明人： Yelehanka Ramachandramurthy Pradeep ,  Tong Chen ,  Zhi Han ,  Zhen Zheng ,  Kelvin Ong ,  Tian Gu ,  Syn Cheah

    IPC分类号： H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/4763 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/6656

    摘要： An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.

    摘要翻译： 提供集成电路。 分别在半导体衬底上和上方提供栅极电介质和栅极。 在栅极电介质附近形成接合部，并且在栅极周围形成成形间隔物。 间隔件形成在成形间隔件下方，衬垫形成在间隔件下方。 第一电介质层形成在半导体衬底，成形间隔物，间隔物，衬垫和栅极上。 在第一电介质层上形成第二电介质层。 局部互连开口形成在第二电介质层中，直到第一电介质层。 打开第一介电层中的局部互连开口以暴露半导体衬底和第一栅极中的结。 第一和第二介电层中的局部互连开口用导电材料填充。

    Method to form and/or isolate vertical transistors
    39.
    发明授权
    Method to form and/or isolate vertical transistors 有权
    形成和/或隔离垂直晶体管的方法

    公开(公告)号：US06511884B1

    公开(公告)日：2003-01-28

    申请号：US09972503

    申请日：2001-10-09

    申请人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

    发明人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

    IPC分类号： H01L21336

    CPC分类号： H01L29/66666 ,  H01L29/7827

    摘要： A method of fabricating an isolated vertical transistor comprising the following steps. A wafer having a first implanted region selected from the group comprising a source region and a drain region is provided. The wafer further includes STI areas on either side of a center transistor area. The wafer is patterned down to the first implanted region to form a vertical pillar within the center transistor area using a patterned hardmask. The vertical pillar having side walls. A pad dielectric layer is formed over the wafer, lining the vertical pillar. A nitride layer is formed over the pad dielectric layer. The structure is patterned and etched through the nitride layer and the pad dielectric layer; and into the wafer within the STI areas to form STI trenches within the wafer. The STI trenches are filled with insulative material to form STIs within STI trenches. The patterned nitride and pad dielectric layers are removed. The patterned hardmask is removed. Gate oxide is grown over the exposed portions of the wafer and the vertical pillar. Spacer gates are formed over the gate oxide lined side walls of the vertical pillar. Spacer gate implants are formed within the spacer gates, and a second implanted region is formed within the vertical pillar selected from the group consisting of a drain region and a source region that is not the same as the first implanted region to complete formation of the isolated vertical transistor.

    摘要翻译： 一种制造隔离垂直晶体管的方法，包括以下步骤。 提供具有从包括源极区域和漏极区域的组中选择的第一注入区域的晶片。 该晶片还包括在中心晶体管区域两侧的STI区域。 将晶片图案化到第一注入区域，以使用图案化的硬掩模在中心晶体管区域内形成垂直柱。 具有侧壁的立柱。 在晶片上形成衬垫介质层，衬在垂直柱上。 在焊盘介电层上形成氮化物层。 该结构被图案化并蚀刻通过氮化物层和焊盘介电层; 并进入STI区域内的晶片，以在晶片内形成STI沟槽。 STI沟槽填充有绝缘材料，以在STI沟槽内形成STI。 图案化的氮化物和焊盘介电层被去除。 去除图案化的硬掩模。 栅极氧化物生长在晶片和垂直柱的暴露部分上。 在垂直柱的栅极氧化物衬里侧壁上形成间隔栅极。 间隔栅极内部形成间隔栅极，并且在垂直柱内形成第二注入区，该垂直柱选自由漏极区域和不同于第一注入区域的源极区域组成的组，以完成孤立的 垂直晶体管。