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24 条记录 (耗时 0.025 秒)

    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks
    5.
    发明授权
    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 有权
    通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程

    公开(公告)号：US07250669B2

    公开(公告)日：2007-07-31

    申请号：US10909523

    申请日：2004-08-02

    申请人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    发明人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    IPC分类号： H01L29/00

    CPC分类号： H01L21/764 ,  H01L21/26506

    摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

    摘要翻译： 降低半导体器件衬底效应的第一种方法包括以下步骤。 选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。 在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。 在所述至少一个上介电层上形成钝化层。 图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。 选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。 减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks
    6.
    发明授权
    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 失效
    通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程

    公开(公告)号：US06869884B2

    公开(公告)日：2005-03-22

    申请号：US10225828

    申请日：2002-08-22

    申请人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    发明人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/302 ,  H01L21/461 ,  H01L21/764

    CPC分类号： H01L21/764 ,  H01L21/26506

    摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

    摘要翻译： 降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。 在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。 在所述至少一个上介电层上形成钝化层。 图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。 选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。 减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

    INTEGRATED CIRCUIT SYSTEM WITH HIERARCHICAL CAPACITOR AND METHOD OF MANUFACTURE THEREOF
    8.
    发明申请
    INTEGRATED CIRCUIT SYSTEM WITH HIERARCHICAL CAPACITOR AND METHOD OF MANUFACTURE THEREOF 有权
    具有分层电容器的集成电路系统及其制造方法

    公开(公告)号：US20100295153A1

    公开(公告)日：2010-11-25

    申请号：US12471007

    申请日：2009-05-22

    申请人： Shao-fu Sanford Chu ,  Shaoqing Zhang ,  Johnny Kok Wai Chew ,  Chit Hwei Ng

    发明人： Shao-fu Sanford Chu ,  Shaoqing Zhang ,  Johnny Kok Wai Chew ,  Chit Hwei Ng

    IPC分类号： H01L29/92 ,  H01L21/02

    CPC分类号： H01L23/5223 ,  H01L27/0207 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers with the second group of metal layers to form a capacitor.

    摘要翻译： 一种制造集成电路系统的方法包括：提供包括前端电路的基板; 利用第一设计规则在所述衬底上形成包括第一手指和第二手指的第一组金属层，所述第一组金属层形成为没有手指通孔; 利用大于第一设计规则的第二设计规则，在第一组金属层上形成包括第一手指，第二手指和手指通孔的第二组金属层; 并且将所述第一组金属层与所述第二组金属层互连以形成电容器。

    Integrated circuit system with hierarchical capacitor and method of manufacture thereof
    9.
    发明授权
    Integrated circuit system with hierarchical capacitor and method of manufacture thereof 有权
    具有层状电容器的集成电路系统及其制造方法

    公开(公告)号：US08021954B2

    公开(公告)日：2011-09-20

    申请号：US12471007

    申请日：2009-05-22

    申请人： Shao-fu Sanford Chu ,  Shaoqing Zhang ,  Johnny Kok Wai Chew ,  Chit Hwei Ng

    发明人： Shao-fu Sanford Chu ,  Shaoqing Zhang ,  Johnny Kok Wai Chew ,  Chit Hwei Ng

    IPC分类号： H01L21/20 ,  H01L21/02

    CPC分类号： H01L23/5223 ,  H01L27/0207 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers with the second group of metal layers to form a capacitor.

    摘要翻译： 一种制造集成电路系统的方法包括：提供包括前端电路的基板; 利用第一设计规则在所述衬底上形成包括第一手指和第二手指的第一组金属层，所述第一组金属层形成为没有手指通孔; 利用大于第一设计规则的第二设计规则，在第一组金属层上形成包括第一手指，第二手指和手指通孔的第二组金属层; 并且将所述第一组金属层与所述第二组金属层互连以形成电容器。