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公开(公告)号：US07109987B2
公开(公告)日：2006-09-19
申请号：US10790952
申请日：2004-03-02
IPC分类号： G06T15/30
CPC分类号： G06T17/20 , G06T15/005 , G06T2200/28
摘要： A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.
摘要翻译： 用于双通道适应性镶嵌的方法和装置包括可操作地耦合以接收原始信息的顶点石斑鱼细分器和索引列表以及耦合到顶点石斑鱼细分器的着色器处理单元。 在第一次通过期间，着色器处理单元接收从原始信息生成的原始索引和多个基元索引中的每一个的自动索引值。 所述方法和装置还包括可操作地耦合到着色器序列的多个顶点着色器输入暂存寄存器，其中多个顶点着色器输入暂存寄存器耦合到多个顶点着色器，使得响应于着色器序列输出，顶点 着色器产生细分因素。 将细分因子提供给顶点分组器细分器，使得顶点分割器细分器在第二遍期间生成每个进程向量输出，每个基元输出和每个分组输出。
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公开(公告)号：US09390554B2
公开(公告)日：2016-07-12
申请号：US13449410
申请日：2012-04-18
CPC分类号： G06T17/20 , G06T15/005
摘要： Embodiments include an apparatus, a computer readable medium and a method for distributing tessellations within an accelerated processing device (APD) including at least two compute units. Embodiments include processing a plurality of patches in a first compute unit using a hull shader to generate hull shader output data. Once generated, hull shader output data is stored to an off-chip memory when tessellation factors associated with the shader program are greater than a configured threshold. Once stored in the off-chip memory, at least a portion of the hull shader output data is dynamically processed using a second compute unit.
摘要翻译： 实施例包括一种装置，计算机可读介质和用于在包括至少两个计算单元的加速处理装置（APD）内分配镶嵌的方法。 实施例包括使用船体着色器在第一计算单元中处理多个补丁以生成船体着色器输出数据。 一旦生成，当与着色器程序相关联的细分因素大于配置的阈值时，将船体着色器输出数据存储到片外存储器中。 一旦存储在片外存储器中，使用第二计算单元动态地处理至少一部分船体着色器输出数据。
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33.发明授权公开(公告)号：US09196079B2
公开(公告)日：2015-11-24
申请号：US13688853
申请日：2012-11-29
申请人： Jian Yang , Huaibing Zhu , Vineet Goel , Yan Li
发明人： Jian Yang , Huaibing Zhu , Vineet Goel , Yan Li
CPC分类号： G06T15/08 , G06T15/04 , G06T17/20 , G06T17/205
摘要： A system, method, and computer program product are provided for tessellation using shaders. New graphics pipeline stages implemented by shaders are introduced, including an inner ring shader, an outer edge shader, and topologic shader, which work together with a domain shader and geometry shader to provide tessellated points and primitives. A hull shader is modified to compute values used by the new shaders to perform tessellation algorithms. This approach provides parallelism and customizability to the presently static tessellation engine implementation.
摘要翻译： 提供了使用着色器进行细分的系统，方法和计算机程序产品。 引入了由着色器实现的新图形流水线阶段，包括内环着色器，外边缘着色器和拓扑着色器，它们与域着色器和几何着色器一起工作，以提供细分点和基元。 修改船体着色器以计算新着色器使用的值来执行镶嵌算法。 这种方法提供了对当前静态细分引擎实现的并行性和可定制性。
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公开(公告)号：US09076260B2
公开(公告)日：2015-07-07
申请号：US13599645
申请日：2012-08-30
申请人： Vineet Goel , Usame Ceylan
发明人： Vineet Goel , Usame Ceylan
IPC分类号： G06T17/20
CPC分类号： G06T17/20 , G06T15/005
摘要： Techniques described in the disclosure are generally related to determining the manner in which to connect points that reside along an outer ring edge and an inner ring edge for purposes of tessellation. For example, a two-dimensional (2D) stitching table may define the manner in which points along the edges should be connected together to form a plurality of primitives. The techniques may index the 2D stitching table to retrieve entry values that define the manner in which the points along the edges should be connected together.
摘要翻译： 本公开中描述的技术通常涉及确定连接沿着外环边缘和内环边缘驻留的点的方式，用于镶嵌的目的。 例如，二维（2D）缝合表可以定义沿着边缘的点应该连接在一起以形成多个图元的方式。 这些技术可能会对2D缝合表进行索引，以检索确定沿着边缘的点应连接在一起的方式的条目值。
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公开(公告)号：US08928679B2
公开(公告)日：2015-01-06
申请号：US13616474
申请日：2012-09-14
申请人： Jason Carroll , Vineet Goel , Mangesh Nijasure , Todd E. Martin
发明人： Jason Carroll , Vineet Goel , Mangesh Nijasure , Todd E. Martin
摘要： A system, method and a computer program product are provided for distributing prim groups for parallel processing in a single clock cycle. A work distributor divides a draw call for primitive processing into a plurality of prim groups according to a prim group size. The work distributor then distributes the plurality of prim groups to a plurality of shader engines for parallel processing of the plurality of prim groups during a clock cycle. The size of a prim group and a number of prim groups are scaled to the plurality of shader engines.
摘要翻译： 提供了一种系统，方法和计算机程序产品，用于在单个时钟周期内分发用于并行处理的初级组。 工作分配器根据初始组大小将原始处理的绘制调用划分为多个初始组。 然后，工作分配器将多个初始组分配到多个着色引擎，用于在时钟周期期间对多个初始组进行并行处理。 原始组的大小和多个prim组的大小被缩放到多个着色器引擎。
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公开(公告)号：US08854374B2
公开(公告)日：2014-10-07
申请号：US13336635
申请日：2011-12-23
IPC分类号： G06T11/20
CPC分类号： G06T17/20
摘要： Methods, systems, and computer readable media embodiments are disclosed for generating primitives in a grid. Embodiments include generating a set of vertices in a section of the grid, selecting one or more vertices in the set of vertices in an order based on a proximity of the vertices to a boundary edge of the grid, and generating primitives based on the order of the selected vertices.
摘要翻译： 公开了用于在网格中生成图元的方法，系统和计算机可读介质实施例。 实施例包括在网格的一部分中生成一组顶点，基于顶点到网格的边界边缘的顺序，以一定顺序选择顶点集合中的一个或多个顶点，并且基于网格的顺序生成图元 所选顶点。
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公开(公告)号：US20140078156A1
公开(公告)日：2014-03-20
申请号：US13616474
申请日：2012-09-14
申请人： Jason Carroll , Vineet Goel , Mangesh Nijasure , Todd E. Martin
发明人： Jason Carroll , Vineet Goel , Mangesh Nijasure , Todd E. Martin
IPC分类号： G06T1/20
摘要： A system, method and a computer program product are provided for distributing prim groups for parallel processing in a single clock cycle. A work distributor divides a draw call for primitive processing into a plurality of prim groups according to a prim group size. The work distributor then distributes the plurality of prim groups to a plurality of shader engines for parallel processing of the plurality of prim groups during a clock cycle. The size of a prim group and a number of prim groups are scaled to the plurality of shader engines.
摘要翻译： 提供了一种系统，方法和计算机程序产品，用于在单个时钟周期内分发用于并行处理的初级组。 工作分配器根据初始组大小将原始处理的绘制调用划分为多个初始组。 然后，工作分配器将多个初始组分配到多个着色引擎，用于在时钟周期期间并行处理多个初始组。 原始组的大小和多个prim组的大小被缩放到多个着色器引擎。
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公开(公告)号：US07423644B2
公开(公告)日：2008-09-09
申请号：US11428756
申请日：2006-07-05
IPC分类号： G06T15/30
CPC分类号： G06T17/20 , G06T15/005 , G06T2200/28
摘要： A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.
摘要翻译： 用于双通道适应性镶嵌的方法和装置包括可操作地耦合以接收原始信息的顶点石斑鱼细分器和索引列表以及耦合到顶点石斑鱼细分器的着色器处理单元。 在第一次通过期间，着色器处理单元接收从原始信息生成的原始索引和多个基元索引中的每一个的自动索引值。 所述方法和装置还包括可操作地耦合到着色器序列的多个顶点着色器输入暂存寄存器，其中多个顶点着色器输入暂存寄存器耦合到多个顶点着色器，使得响应于着色器序列输出，顶点 着色器产生细分因素。 将细分因子提供给顶点分组器细分器，使得顶点分割器细分器在第二遍期间生成每个进程向量输出，每个基元输出和每个分组输出。
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39.发明申请Techniques for storing real-time voice messages in a caller's voicemail box 有权用于在呼叫者的语音邮箱中存储实时语音消息的技术公开(公告)号：US20070286356A1
公开(公告)日：2007-12-13
申请号：US11448286
申请日：2006-06-07
申请人： Vineet Goel , Aseem Asthana , Ashish Chotai , Sravan Vadlakonda
发明人： Vineet Goel , Aseem Asthana , Ashish Chotai , Sravan Vadlakonda
IPC分类号： H04M1/64
CPC分类号： H04M3/53366 , H04M3/53325 , H04M2203/4554
摘要： Techniques for storing voicemails in real-time in a caller's voicemail system when a voicemail is left in a callee's voicemail system are provided. A connection to the callee's voicemail system is detected during a call from the caller to the callee. When a voicemail is being left on the caller's voicemail system, a copy of the voicemail message is automatically forked to the caller's voicemail system. Thus, when a voicemail message is recorded on the callee's voicemail system, a copy of the voicemail message is also stored on the caller's voicemail system.
摘要翻译： 提供了当在被叫方的语音邮件系统中留下语音邮件时，在呼叫者的语音邮件系统中实时存储语音邮件的技术。 在从呼叫者到被叫者的呼叫期间，检测到被叫者的语音邮件系统的连接。 当主叫方的语音邮件系统上留下语音信箱时，语音邮件消息的副本会自动分配给主叫方的语音邮件系统。 因此，当被叫者的语音邮件系统上记录语音邮件消息时，语音邮件消息的副本也存储在呼叫者的语音邮件系统上。
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公开(公告)号：US20060050072A1
公开(公告)日：2006-03-09
申请号：US11161669
申请日：2005-08-11
申请人： Vineet Goel
发明人： Vineet Goel
CPC分类号： G06T17/20
摘要： A hardware tessellation circuit serves as a unified hardware parametric coordinate generator for providing parametric coordinates for tessellation. The tessellation circuit includes control logic that receives tessellation instruction information, such as an instruction indicating which type of multiple tessellation operations to perform, on an incoming primitive wherein the different types of tessellation include discrete tessellation, continuous tessellation and adaptive tessellation. The tessellation circuit also includes shared tessellation logic that is controlled by the control logic, and includes a plurality of shared logic units, such as arithmetic logic units, that are controllable by the control logic based on the type of tessellation detected to be used for the incoming primitive. The shared tessellation logic is controlled to reuse at least some of the logic units for two different tessellation operations defined by the tessellation type information.
摘要翻译： 硬件细分电路用作统一的硬件参数坐标发生器，用于提供镶嵌的参数坐标。 细分电路包括控制逻辑，该控制逻辑接收镶嵌指令信息，诸如指示要执行哪种类型的多个镶嵌操作的指令，其中不同类型的镶嵌包括离散镶嵌，连续镶嵌和自适应镶嵌。 细分电路还包括由控制逻辑控制的共享镶嵌逻辑，并且包括多个共享逻辑单元，例如算术逻辑单元，其可由控制逻辑基于被检测为用于 传入原始 控制共享的镶嵌逻辑以重用至少一些逻辑单元用于由细分类型信息定义的两个不同的镶嵌操作。
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