公开(公告)号：US20250098199A1

公开(公告)日：2025-03-20

申请号：US18471003

申请日：2023-09-20

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Evan Bertrue Jones ,  Daniel Kevin Etter

IPC: H01L29/778 ,  H01L29/16 ,  H01L29/20 ,  H01L29/40 ,  H01L29/45 ,  H01L29/872

Abstract: Semiconductor devices are provided. In one example, the semiconductor device includes a wide bandgap semiconductor structure. The semiconductor device includes a metal structure on the wide bandgap semiconductor structure. The metal structure has a metal layer. The metal layer has a metal selected from the group consisting of ruthenium, osmium, rhodium, or iridium.

公开(公告)号：US20240429314A1

公开(公告)日：2024-12-26

申请号：US18340471

申请日：2023-06-23

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Michael Lee Schuette ,  James Scott Tweedie ,  Scott Sheppard

IPC: H01L29/778 ,  H01L29/16 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

Abstract: Semiconductor devices are provided. In one example, a semiconductor device includes a Group III-nitride semiconductor structure. The semiconductor device includes a first contact on the Group III-nitride semiconductor structure. The semiconductor device includes a second contact on the Group III-nitride semiconductor structure. The second contact is spaced apart from the first contact. The Group III-nitride semiconductor structure includes a plurality of channel structures extending in a length direction between the first contact and the second contact. The semiconductor device includes an isolation implant region extending along at least a portion of a length of at least one of the plurality of channel structures. The isolation implant region comprises implanted dopants.

公开(公告)号：US20240429120A1

公开(公告)日：2024-12-26

申请号：US18340503

申请日：2023-06-23

Applicant: Wolfspeed, Inc.

Inventor： Michael Lee Schuette ,  KyoungKeun Joseph Lee ,  Matthew R. King ,  Christer Hallin ,  Fabian Radulescu ,  Thomas Albert Kuhr ,  Scott Sheppard ,  James Scott Tweedie ,  Kyle Bothe

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/31 ,  H01L23/373 ,  H01L23/48 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: Semiconductor devices are provided. In one example, a semiconductor device includes a Group III-nitride semiconductor structure. The semiconductor device may include a gate contact on the Group III-nitride semiconductor structure. The semiconductor device may include a field plate overlapping the Group III-nitride semiconductor structure. The semiconductor device may include a thermally conductive passivation layer overlapping the gate contact. The thermally conductive passivation layer may be between the field plate and the Group III-nitride semiconductor structure. The thermally conductive passivation layer may contact the Group III-nitride semiconductor structure. The thermally conductive passivation layer may have a thermal conductivity of at least about 80 W/(m·k).

公开(公告)号：US20240290847A1

公开(公告)日：2024-08-29

申请号：US18175231

申请日：2023-02-27

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Chris Hardiman ,  Scott Sheppard

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/408 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: Semiconductor devices having nitrogen-polar (N-polar) Group III-nitride semiconductor structures are provided. In one example, a semiconductor device may include a nitrogen polar (N-polar) Group III-nitride semiconductor structure. The N-polar Group III-nitride semiconductor structure may have a first surface and a second surface opposing the first surface. The semiconductor device may include an electrode. The semiconductor device may include a low-k dielectric layer located between the first surface of the N-polar Group III-nitride semiconductor structure and at least a portion of the electrode. The low-k dielectric layer may have a dielectric constant of less than about 3.9. In some examples, the N-polar Group III-nitride semiconductor structure may include a trench extending at least partially into one or more cap layers of the N-polar Group III-nitride semiconductor structure.

公开(公告)号：US20240274507A1

公开(公告)日：2024-08-15

申请号：US18168985

申请日：2023-02-14

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Chris Hardiman ,  Scott Sheppard

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5283 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786

Abstract: Semiconductor devices are provided. In one example, a semiconductor device includes a substrate. The semiconductor device includes a nitrogen-polar (N-polar) Group III-nitride semiconductor structure on the substrate. The semiconductor device includes a via passing through the substrate and the N-polar Group III-nitride semiconductor structure. A cross-sectional profile of the via changes at an interface between the substrate and the N-polar Group III-nitride semiconductor structure.

公开(公告)号：US20240105824A1

公开(公告)日：2024-03-28

申请号：US17951711

申请日：2022-09-23

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Christer Hallin ,  Helder Jose DaSilva Antunes

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/413 ,  H01L29/1608

Abstract: Transistor devices are provided. In one example, the transistor device includes a channel layer. The transistor device includes a multilayer barrier structure on the channel layer. The transistor device includes a gate contact having a gate length of about 100 nm or less. A ratio of the gate length to a thickness of the multilayer barrier structure is in a range of about 8:1 to about 16:1.

公开(公告)号：US20240105823A1

公开(公告)日：2024-03-28

申请号：US17951708

申请日：2022-09-23

Applicant: Wolfspeed, Inc.

Inventor： Jia Guo ,  Kyle Bothe ,  Olof Tornblad ,  Scott Sheppard

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/1608

Abstract: Transistor devices are provided. In one example, the transistor device includes a channel layer. The transistor device includes a multilayer barrier structure on the channel layer. The multilayer barrier structure includes a first Group III-nitride layer and a second Group III-nitride layer on the first Group III-nitride layer and opposite to the channel layer. The first Group III-nitride layer has a thickness greater than a thickness of the second Group III-nitride layer. An aluminum concentration of the first Group III-nitride layer is at least two times greater than an aluminum concentration of the second Group III-nitride layer.

公开(公告)号：US20240072125A1

公开(公告)日：2024-02-29

申请号：US17893277

申请日：2022-08-23

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Evan Jones ,  Chris Hardiman

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/04 ,  H01L21/285 ,  H01L29/16 ,  H01L29/20 ,  H01L29/45

CPC classification number: H01L29/401 ,  H01L21/0217 ,  H01L21/0485 ,  H01L21/28575 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/45 ,  H01L29/452

Abstract: A method of forming ohmic contacts on a semiconductor layer includes forming silicon ohmic contact precursors on the semiconductor layer, depositing a layer of metal on the semiconductor layer including the silicon ohmic contact precursors, reacting the layer of metal with the silicon ohmic contact precursors to form metal silicide ohmic contacts on the semiconductor layer, and selectively removing the layer of metal from the semiconductor layer without removing the metal silicide contacts from the semiconductor layer.

公开(公告)号：US11502178B2

公开(公告)日：2022-11-15

申请号：US17081476

申请日：2020-10-27

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Jia Guo ,  Terry Alcorn ,  Fabian Radulescu ,  Scott Sheppard

IPC: H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778

Abstract: A transistor device includes a semiconductor layer, a surface dielectric layer on the semiconductor layer, and at least a portion of a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The transistor device includes an interlayer dielectric layer on the surface dielectric layer, and a field plate on the interlayer dielectric layer. The field plate is laterally spaced apart from the gate, and at least a portion of the field plate includes a recessed portion above the aperture in the surface dielectric layer.