公开(公告)号：US20240304702A1

公开(公告)日：2024-09-12

申请号：US18179070

申请日：2023-03-06

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Chris Hardiman ,  Scott Sheppard

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/4232 ,  H01L29/7786

Abstract: Field reducing structures for transistor devices having Group III-nitride semiconductor structures are provided. In one example, a transistor device includes a nitrogen-polar (N-polar) Group III-nitride semiconductor structure. The transistor device includes a source contact, a drain contact, and a gate contact. The transistor device includes a field reducing structure operable to reduce an electric field in a region in the N-polar Group III-nitride semiconductor structure between the gate contact and the drain contact.

公开(公告)号：US11616136B2

公开(公告)日：2023-03-28

申请号：US17180048

申请日：2021-02-19

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Evan Jones ,  Dan Namishia ,  Chris Hardiman ,  Fabian Radulescu ,  Terry Alcorn ,  Scott Sheppard ,  Bruce Schmukler

IPC: H01L21/00 ,  H01L29/08 ,  H01L29/778 ,  H01L21/285 ,  H01L21/306 ,  H01L21/765 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H03F1/02 ,  H03F3/21

Abstract: A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.

公开(公告)号：US20240063300A1

公开(公告)日：2024-02-22

申请号：US17890453

申请日：2022-08-18

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Chris Hardiman ,  Elizabeth Keenan ,  Jia Guo ,  Fabian Radulescu ,  Scott Sheppard

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/417

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/41725

Abstract: A high electron mobility transistor comprises a semiconductor layer structure that includes a channel layer and a barrier layer and source and drain contacts on the semiconductor layer structure. A gate contact and a multi-layer passivation structure are provided on the semiconductor layer structure between the source contact and the drain contact. The multi-layer passivation structure comprises at least first and second silicon nitride layers that have different material compositions. A spacer passivation layer is provided on sidewalls of the first and second silicon nitride layers. A material composition of the spacer passivation layer is different than a material composition of at least one of the layers of the multi-layer passivation structure.

公开(公告)号：US20240194751A1

公开(公告)日：2024-06-13

申请号：US18063787

申请日：2022-12-09

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Chris Hardiman ,  Chloe Hawes ,  Daniel Namishia ,  Evan Jones

IPC: H01L29/417 ,  H01L23/66 ,  H01L29/40

CPC classification number: H01L29/41783 ,  H01L23/66 ,  H01L29/401 ,  H01L29/7786

Abstract: A transistor device includes a semiconductor structure having an implanted region adjacent a surface thereof; and a source/drain contact including an ohmic contact portion on the implanted region of the semiconductor structure. The implanted region laterally extends beyond the ohmic contact portion by less than about 0.8 microns, e.g., by less than about 0.2 microns or such that a boundary of the implanted region is substantially aligned with an edge of the ohmic contact portion. Related fabrication methods are also discussed.

公开(公告)号：US20230395670A1

公开(公告)日：2023-12-07

申请号：US17834144

申请日：2022-06-07

Applicant: Wolfspeed, Inc.

Inventor： Chris Hardiman ,  Kyoung-Keun Lee ,  Kyle Bothe ,  Fabian Radulescu

IPC: H01L29/423 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/285 ,  H01L29/66

CPC classification number: H01L29/42316 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786 ,  H01L21/28581 ,  H01L29/66462

Abstract: A transistor device includes a semiconductor structure comprising a channel layer and a barrier layer; source and drain contacts on the semiconductor structure; and a gate on the semiconductor structure between the source and drain contacts. A first portion of the barrier layer extending between the source or drain contact and the gate has a first thickness, a second portion of the barrier layer between the gate and the channel layer has a second thickness, and the first thickness is about 1.5 times to 4 times greater than the second thickness. Related methods of fabrication using a looped recess process are also discussed.

公开(公告)号：US20240429230A1

公开(公告)日：2024-12-26

申请号：US18337657

申请日：2023-06-20

Applicant: Wolfspeed, Inc.

Inventor： Matthew King ,  Chris Hardiman ,  Kyle Bothe ,  Jeremy Fisher

IPC: H01L27/06 ,  H01L21/8252 ,  H01L23/66 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: A semiconductor device includes a semiconductor structure comprising first and second semiconductor layers having different bandgaps, first and second contacts on the semiconductor structure and free of a gate structure therebetween, and a resistor comprising a portion of the semiconductor structure that electrically connects the first and second contacts. The portion of the semiconductor structure may be a second portion of the second semiconductor layer that is recessed in thickness relative to a first portion thereof, and/or may include a passivation layer in direct contact with the second semiconductor layer. Related devices, packages, and fabrication methods are discussed.

公开(公告)号：US20240421193A1

公开(公告)日：2024-12-19

申请号：US18333632

申请日：2023-06-13

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Jia Guo ,  Christer Hallin ,  Alexander V. Suvorov ,  Chris Hardiman ,  Scott Sheppard

IPC: H01L29/20 ,  H01L29/205 ,  H01L29/45 ,  H01L29/66 ,  H01L29/778

Abstract: Semiconductor devices with reduced contact resistance of ohmic contacts are provided. In one example, the semiconductor device includes a Group III-nitride semiconductor structure. The Group III-nitride semiconductor structure includes a channel layer and a barrier layer on the channel layer. The semiconductor device includes an implanted region extending into the channel layer. The implanted region includes a distribution of implanted dopants. The semiconductor device includes a recess in the implanted region. The recess extends through the barrier layer into the channel layer. The semiconductor device includes an ohmic contact within the recess.

公开(公告)号：US20240290876A1

公开(公告)日：2024-08-29

申请号：US18173534

申请日：2023-02-23

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Chris Hardiman ,  Scott Sheppard

IPC: H01L29/778 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66462

Abstract: Semiconductor device having nitrogen-polar (N-polar) Group III-nitride structures are provided. In one example, a semiconductor device may include an N-polar Group III-nitride semiconductor structure. The N-polar Group III-nitride semiconductor structure may have a first region and a second region. The N-polar Group III-nitride semiconductor structure may have a first surface and a second surface opposing the first surface. The second surface may be a planar surface. The semiconductor device may include an isolation implant region extending from the second surface into the N-polar Group III-nitride semiconductor structure to a depth sufficient to provide electrical isolation between the first region and the second region of the N-polar Group III-nitride semiconductor structure.

公开(公告)号：US20230395695A1

公开(公告)日：2023-12-07

申请号：US18310684

申请日：2023-05-02

Applicant: Wolfspeed, Inc.

Inventor： Chris Hardiman ,  Matthew King ,  Kyle Bothe

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L29/40 ,  H01L21/3065 ,  H01J37/32

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/7786 ,  H01L29/407 ,  H01L21/3065 ,  H01J37/321 ,  H01J2237/334

Abstract: A transistor device includes a semiconductor structure comprising a channel layer and a barrier layer, source and drain contacts on the semiconductor structure, and a conductive element in a recess in the barrier layer between the source and drain contacts. The barrier layer has a first thickness adjacent the source or drain contact, a second thickness at a floor of the recess between the conductive element and the channel layer, and the first thickness is about 1.2 times to 4 times greater than the second thickness. Related methods of fabrication using a looped recess process are also discussed.

公开(公告)号：US11587842B2

公开(公告)日：2023-02-21

申请号：US17083712

申请日：2020-10-29

Applicant: Wolfspeed, Inc.

Inventor： Chris Hardiman ,  Kyoung-Keun Lee ,  Fabian Radulescu ,  Daniel Namishia ,  Scott Thomas Sheppard

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/31 ,  H01L29/06 ,  H01L21/56 ,  H01L23/532 ,  H01L23/00 ,  H01L29/20

Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.