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公开(公告)号:US12266721B2
公开(公告)日:2025-04-01
申请号:US17834013
申请日:2022-06-07
Applicant: Wolfspeed, Inc.
Inventor: Jia Guo , Kyle Bothe , Scott Sheppard
IPC: H01L29/778 , H01L29/40 , H01L29/66
Abstract: A transistor device according to some embodiments includes a semiconductor barrier layer, a surface dielectric layer on the semiconductor barrier layer, and a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The device includes an interlayer dielectric layer on the surface dielectric layer that extends over the gate and into the aperture in the surface dielectric layer, and a multiple-stepped field plate on the interlayer dielectric layer. The multiple-stepped field plate is laterally spaced apart from the gate. A recessed portion of the multiple-stepped field plate is above the aperture in the surface dielectric layer, and the multiple-stepped field plate includes a first step adjacent the recessed portion of the field plate on a side of the field plate opposite the gate, and a second step adjacent the first step.
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公开(公告)号:US12218202B2
公开(公告)日:2025-02-04
申请号:US17477004
申请日:2021-09-16
Applicant: Wolfspeed, Inc.
Inventor: Evan Jones , Saptha Sriram , Kyle Bothe
IPC: H01L29/778 , H01L29/10
Abstract: A semiconductor device includes a substrate having an upper surface including a recess region, a semiconductor structure on the substrate, a portion of the semiconductor structure within the recess region, and a gate contact, a drain contact, and a source contact on the semiconductor structure. The recess region does not vertically overlap the drain contact or the source contact.
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公开(公告)号:US20240304702A1
公开(公告)日:2024-09-12
申请号:US18179070
申请日:2023-03-06
Applicant: Wolfspeed, Inc.
Inventor: Kyle Bothe , Chris Hardiman , Scott Sheppard
IPC: H01L29/66 , H01L29/20 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/778
CPC classification number: H01L29/66462 , H01L29/2003 , H01L29/402 , H01L29/41725 , H01L29/4232 , H01L29/7786
Abstract: Field reducing structures for transistor devices having Group III-nitride semiconductor structures are provided. In one example, a transistor device includes a nitrogen-polar (N-polar) Group III-nitride semiconductor structure. The transistor device includes a source contact, a drain contact, and a gate contact. The transistor device includes a field reducing structure operable to reduce an electric field in a region in the N-polar Group III-nitride semiconductor structure between the gate contact and the drain contact.
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公开(公告)号:US20240178311A1
公开(公告)日:2024-05-30
申请号:US18071768
申请日:2022-11-30
Applicant: Wolfspeed, Inc.
Inventor: Kyle Bothe , Satyaki Ganguly
IPC: H01L29/778 , H01L29/40
CPC classification number: H01L29/7786 , H01L29/402
Abstract: Transistor devices are provided. In one example, a transistor device includes a Group III nitride-based semiconductor structure. The transistor device has a non-degradation time of at least about 350 hours without degrading an output power of the transistor device by 1 dB or greater during a test condition. The test condition is associated with an operating frequency of the transistor device of about 31.5 GHz and a junction temperature of the transistor device of about 380° ° C.
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公开(公告)号:US11616136B2
公开(公告)日:2023-03-28
申请号:US17180048
申请日:2021-02-19
Applicant: Wolfspeed, Inc.
Inventor: Kyle Bothe , Evan Jones , Dan Namishia , Chris Hardiman , Fabian Radulescu , Terry Alcorn , Scott Sheppard , Bruce Schmukler
IPC: H01L21/00 , H01L29/08 , H01L29/778 , H01L21/285 , H01L21/306 , H01L21/765 , H01L29/20 , H01L29/205 , H01L29/40 , H01L29/417 , H01L29/45 , H01L29/66 , H03F1/02 , H03F3/21
Abstract: A power amplifier comprising a GaN-based high electron mobility transistor (HEMT) device, wherein a power added efficiency (PAE) of the power amplifier is greater than 32% at P1DB during operation of the power amplifier between 26.5 GHz and 30.5 GHz.
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公开(公告)号:US20220328634A1
公开(公告)日:2022-10-13
申请号:US17848984
申请日:2022-06-24
Applicant: Wolfspeed, Inc.
Inventor: Kyle Bothe , Jia Guo , Yueying Liu , Jeremy Fisher , Scott T. Sheppard
IPC: H01L29/20 , H01L29/778 , H01L29/40 , H01L29/423
Abstract: A transistor device includes a first unit subcell including having a first active region width extending in a first direction, and a second unit subcell having a second active region width extending in the first direction and arranged adjacent the first unit subcell in the first direction. The first unit subcell and the second unit subcell share a common drain contact and have separate gate contacts that are aligned in the first direction. Each unit subcell includes a field plate that is connected to a source contact outside the active region and that does not cross over the gate contact.
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公开(公告)号:US12113114B2
公开(公告)日:2024-10-08
申请号:US17508846
申请日:2021-10-22
Applicant: Wolfspeed, Inc.
Inventor: Kyle Bothe , Evan Jones
IPC: H01L29/778 , H01L29/20 , H01L29/45
CPC classification number: H01L29/452 , H01L29/2003 , H01L29/7786
Abstract: A transistor includes a semiconductor layer and a channel region. The transistor further includes a first doped contact region in the semiconductor layer and adjacent the channel region. The transistor further includes a first ohmic contact including an interface region comprising a first interface length between the first ohmic contact and the first doped contact region larger than a length of the interface region.
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8.
公开(公告)号:US20240313099A1
公开(公告)日:2024-09-19
申请号:US18121782
申请日:2023-03-15
Applicant: Wolfspeed, Inc.
Inventor: Kyle Bothe , Evan Jones , Daniel Etter
IPC: H01L29/778 , H01L29/20 , H01L29/423 , H01L29/872
CPC classification number: H01L29/7786 , H01L29/2003 , H01L29/4232 , H01L29/872
Abstract: A transistor device includes a semiconductor body and a non-ohmic contact on the semiconductor body. The non-ohmic contact includes a phonon scattering layer on the semiconductor body, a protection layer on a surface of the phonon scattering layer opposite the semiconductor body, and a contact layer on a surface of the protection layer opposite the phonon scattering layer. The phonon scattering layer has a work function in a range of about 4.5 eV to about 5.7 eV and a melting point in a range of about 1550° C. to about 3200° C.
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公开(公告)号:US20240266419A1
公开(公告)日:2024-08-08
申请号:US18164205
申请日:2023-02-03
Applicant: Wolfspeed, Inc.
Inventor: Matthew R. King , Kyle Bothe , Christer Hallin
IPC: H01L29/66 , H01L29/04 , H01L29/16 , H01L29/20 , H01L29/778
CPC classification number: H01L29/66462 , H01L29/045 , H01L29/1608 , H01L29/2003 , H01L29/7786
Abstract: Semiconductor devices are provided. In one example, a semiconductor device includes a substrate. The semiconductor device includes a polarity inverting layer on the substrate. The semiconductor device includes a nitrogen-polar (N-Polar) Group III-nitride semiconductor structure on the polarity inverting layer.
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10.
公开(公告)号:US20240194751A1
公开(公告)日:2024-06-13
申请号:US18063787
申请日:2022-12-09
Applicant: Wolfspeed, Inc.
Inventor: Kyle Bothe , Chris Hardiman , Chloe Hawes , Daniel Namishia , Evan Jones
IPC: H01L29/417 , H01L23/66 , H01L29/40
CPC classification number: H01L29/41783 , H01L23/66 , H01L29/401 , H01L29/7786
Abstract: A transistor device includes a semiconductor structure having an implanted region adjacent a surface thereof; and a source/drain contact including an ohmic contact portion on the implanted region of the semiconductor structure. The implanted region laterally extends beyond the ohmic contact portion by less than about 0.8 microns, e.g., by less than about 0.2 microns or such that a boundary of the implanted region is substantially aligned with an edge of the ohmic contact portion. Related fabrication methods are also discussed.
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