Field effect transistor with multiple stepped field plate

    公开(公告)号:US12266721B2

    公开(公告)日:2025-04-01

    申请号:US17834013

    申请日:2022-06-07

    Abstract: A transistor device according to some embodiments includes a semiconductor barrier layer, a surface dielectric layer on the semiconductor barrier layer, and a gate on the surface dielectric layer. The surface dielectric layer includes an aperture therein that is laterally spaced apart from the gate. The device includes an interlayer dielectric layer on the surface dielectric layer that extends over the gate and into the aperture in the surface dielectric layer, and a multiple-stepped field plate on the interlayer dielectric layer. The multiple-stepped field plate is laterally spaced apart from the gate. A recessed portion of the multiple-stepped field plate is above the aperture in the surface dielectric layer, and the multiple-stepped field plate includes a first step adjacent the recessed portion of the field plate on a side of the field plate opposite the gate, and a second step adjacent the first step.

    Semiconductor device incorporating a substrate recess

    公开(公告)号:US12218202B2

    公开(公告)日:2025-02-04

    申请号:US17477004

    申请日:2021-09-16

    Abstract: A semiconductor device includes a substrate having an upper surface including a recess region, a semiconductor structure on the substrate, a portion of the semiconductor structure within the recess region, and a gate contact, a drain contact, and a source contact on the semiconductor structure. The recess region does not vertically overlap the drain contact or the source contact.

    High Frequency, High Temperature Transistor Devices

    公开(公告)号:US20240178311A1

    公开(公告)日:2024-05-30

    申请号:US18071768

    申请日:2022-11-30

    CPC classification number: H01L29/7786 H01L29/402

    Abstract: Transistor devices are provided. In one example, a transistor device includes a Group III nitride-based semiconductor structure. The transistor device has a non-degradation time of at least about 350 hours without degrading an output power of the transistor device by 1 dB or greater during a test condition. The test condition is associated with an operating frequency of the transistor device of about 31.5 GHz and a junction temperature of the transistor device of about 380° ° C.

    FIELD EFFECT TRANSISTOR WITH STACKED UNIT SUBCELL STRUCTURE

    公开(公告)号:US20220328634A1

    公开(公告)日:2022-10-13

    申请号:US17848984

    申请日:2022-06-24

    Abstract: A transistor device includes a first unit subcell including having a first active region width extending in a first direction, and a second unit subcell having a second active region width extending in the first direction and arranged adjacent the first unit subcell in the first direction. The first unit subcell and the second unit subcell share a common drain contact and have separate gate contacts that are aligned in the first direction. Each unit subcell includes a field plate that is connected to a source contact outside the active region and that does not cross over the gate contact.

    Transistor with ohmic contacts
    7.
    发明授权

    公开(公告)号:US12113114B2

    公开(公告)日:2024-10-08

    申请号:US17508846

    申请日:2021-10-22

    CPC classification number: H01L29/452 H01L29/2003 H01L29/7786

    Abstract: A transistor includes a semiconductor layer and a channel region. The transistor further includes a first doped contact region in the semiconductor layer and adjacent the channel region. The transistor further includes a first ohmic contact including an interface region comprising a first interface length between the first ohmic contact and the first doped contact region larger than a length of the interface region.

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